Quantum-dot cellular automata (QCA) is an alternative nanotechnology to traditional CMOS technology. In theory, circuits in QCA have the advantages of lower power consumption, higher integration density and switching frequency than circuits based on CMOS. Random access memory (RAM) circuits that are critical in designing large memory circuits have been explored. In this brief, a novel loop-based RAM cell with asynchronous set and reset, by using a new 2-1 multiplexer and D-latch, is proposed. Efficient 1×4 RAM and 4×4 RAM with three-layer structure are constructed. The proposed RAM cell has 35% improvement in both circuit footprint and cost, compared with an existing best scheme. The 1×4 RAM has less cells, delay and area than the previous designs with the same circuit scheme. The 4×4 RAM and m×n RAM show that the proposed RAM cell has excellent scalability for designing complex circuits. Functional correctness of the proposed designs has been proved by using QCADesigner 2.0.3.

In background subtraction tasks, spatial and temporal contexts are beneficial in detecting moving objects. The methods based on Deep Neural Networks in this task has explored different topologies, which are composed of the conventional operations of convolutional neural networks, such as Convolutional Long-short Term Memory layer (ConvLSTM), 2D convolutional layer, or 3D convolutional layer, to capture these contexts. In this work, we propose a new background subtraction algorithm named spatial–temporal propagation network. An end-to-end network with novel layers, whose process of operation is equivalent to that the feature maps multiply with affinity matrices, is proposed to capture the spatial–temporal correlation in video sequences and aggregate the deep features from the consecutive frames. Experimental results on CDnet-2014 and LASIESTA datasets show that this novel layer provides an alternative way for our network to aggregate multiscale spatial–temporal features. Meanwhile, the proposed network achieves state-of-the-art performance and is generalizable to unseen videos.

Deterministic approaches have recently been developed for accurate computation in stochastic computing (SC). They, however, suffer a long operation time. Fortunately, for applications that do not require completely accurate processing results, such as image processing, the time can significantly be reduced due to the better progressive precision in the bit-streams generated by these approaches. That means a computation can be terminated in time when its output accuracy is acceptable. Due to the fast convergence property of low-discrepancy sequences, we propose three deterministic Halton sequence (DHS)-based stochastic number generators (SNGs) for the first time by using, respectively, prime length, rotation, and clock division for accelerating computation in SC. Experimental results show that the proposed designs are more efficient than their counterparts. For multiplication, the proposed DHS-based designs perform up to $32\times $ faster than prior designs for a mean error of 0.1%. The speedup reaches $128\times $ for an edge detection algorithm. Three stochastic circuits are then designed by using the proposed DHS-based SNGs for the Bernsen binarization algorithm, which lead to more accurate results than existing designs at the same bit-stream length. Finally, the proposed designs show an excellent fault-tolerance against bit flipping errors.