Quantum dot cellular automata (QCA) is considered one of the most promising technologies to replace the current CMOS technology. Compared with the traditional transistor technology, the computation relies on a new paradigm based on the interaction between nearby QCA cells. It has significant advantages, such as operating frequency (THz), high device density, and low power consumption. In this paper, a novel XOR/XNOR-function logic gate with two inputs, two enable inputs and one output is proposed and designed in Quantum-dot Cellular Automata (QCA) nanotechnology. In order to demonstrate the functionality and capabilities of the proposed QCAbased XOR/XNOR architecture, performance is evaluated and analyzed. The proposed XOR/XNOR logic gate has a superb performance in terms of area, complexity, power consumption and cost function in comparison to some existing QCA-based XOR architectures. Moreover, some efficient circuits based on the proposed XOR/XNOR gate are designed in QCA.

Quantum-dot cellular automata (QCA) is an alternative nanotechnology to traditional CMOS technology. In theory, circuits in QCA have the advantages of lower power consumption, higher integration density and switching frequency than circuits based on CMOS. Random access memory (RAM) circuits that are critical in designing large memory circuits have been explored. In this brief, a novel loop-based RAM cell with asynchronous set and reset, by using a new 2-1 multiplexer and D-latch, is proposed. Efficient 1×4 RAM and 4×4 RAM with three-layer structure are constructed. The proposed RAM cell has 35% improvement in both circuit footprint and cost, compared with an existing best scheme. The 1×4 RAM has less cells, delay and area than the previous designs with the same circuit scheme. The 4×4 RAM and m×n RAM show that the proposed RAM cell has excellent scalability for designing complex circuits. Functional correctness of the proposed designs has been proved by using QCADesigner 2.0.3.

Quantum-dot Cellular Automata (QCA) is potentially a very attractive alternative to CMOS for future digital designs. Circuit designs in QCA have been extensively studied. QCA technology has been extensively investigated in recent years. However, only limited attention has been paid to QCA decimal arithmetic. In this paper, an efficient full adder is presented. The layout of the proposed circuit uses 30 QCA cells and a 25% improvement over the best previous design. It has significant improvements in comparison to the previous designs in terms of the number of cells, area and cost and has a similar delay to the fastest previous design. In Ripple Carry Adder (RCA) design, they also maintain high performance. And all of the multi-bit RCA also have the lowest overall cost with a reduction of over 50% when compared with the previous RCA design.