Quantum-dot cellular automata (QCA) is an alternative nanotechnology to traditional CMOS technology. In theory, circuits in QCA have the advantages of lower power consumption, higher integration density and switching frequency than circuits based on CMOS. Random access memory (RAM) circuits that are critical in designing large memory circuits have been explored. In this brief, a novel loop-based RAM cell with asynchronous set and reset, by using a new 2-1 multiplexer and D-latch, is proposed. Efficient 1×4 RAM and 4×4 RAM with three-layer structure are constructed. The proposed RAM cell has 35% improvement in both circuit footprint and cost, compared with an existing best scheme. The 1×4 RAM has less cells, delay and area than the previous designs with the same circuit scheme. The 4×4 RAM and m×n RAM show that the proposed RAM cell has excellent scalability for designing complex circuits. Functional correctness of the proposed designs has been proved by using QCADesigner 2.0.3.

In background subtraction tasks, spatial and temporal contexts are beneficial in detecting moving objects. The methods based on Deep Neural Networks in this task has explored different topologies, which are composed of the conventional operations of convolutional neural networks, such as Convolutional Long-short Term Memory layer (ConvLSTM), 2D convolutional layer, or 3D convolutional layer, to capture these contexts. In this work, we propose a new background subtraction algorithm named spatial–temporal propagation network. An end-to-end network with novel layers, whose process of operation is equivalent to that the feature maps multiply with affinity matrices, is proposed to capture the spatial–temporal correlation in video sequences and aggregate the deep features from the consecutive frames. Experimental results on CDnet-2014 and LASIESTA datasets show that this novel layer provides an alternative way for our network to aggregate multiscale spatial–temporal features. Meanwhile, the proposed network achieves state-of-the-art performance and is generalizable to unseen videos.

A Ka-band differential variable gain amplifier (VGA) applying symmetrical unit arrays with 6-bit digital-controlled is presented. The proposed VGA, based on the conventional current steering theory, uses symmetrical unit arrays that keep the output impedance constant, while digital-controlled voltage changes. Then it combines neutralizing capacitances to counteract the Miller effect of parasitic capacitances between gain and drain of input transistors. The VGA with symmetrical unit arrays ensures the consistency of phase variation during gain fluctuation. The VGA is fabricated in a 65-nm CMOS technology, and achieves −20.2 to −4.2 dB gain varied with 1.52 dBm IP1dB as well as 8.6 dB noise figure at 36 GHz and less than 4.9° phase variation, while consuming 15.6 mW across 30.5–39 GHz frequency range.

The duty cycle in DPWM whose time resolution is as high as hundreds of picosecond will be increased since the propagation delays of internal logics and interconnects are superimposed on the on-time. The duty-cycle-increment phenomenon affects the regulation performance of converter, especially when the delays are the same magnitude level as switching period. In this paper, a compensation method based on tool command language (TCL) commands is used to offset the propagation delays. Furthermore, the DPWM applies counter, phase-locked loop (PLL) and carry chain to constitute segmented delay-line, while maintains a wide duty cycle range and a high time resolution. This DPWM is implemented by a low-cost FPGA Cyclone IV. It achieves a good linearity where $\text{R}^{2}$ is 0.9949 for an 11-bit, 9.375MHz switching frequency DPWM. The duty cycle range is from 1.52% to 97.81%. Meanwhile, the time resolution and average duty difference are 53ps and 3.08%, respectively.

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical path is optimized by a novel synchronous phase-shifted circuit. A carry chain-based delay line is also utilized to improve time resolution. A 14-bit DPWM with the proposed architecture is implemented and tested by Altera Cyclone IV FPGA. The experiment results show that the DPWM achieves high linearity, where R² maintains over 0.9994. Besides, the output duty cycle covers a wide range from 0.9429% to 99.2% and the time resolution is about 41.3ps.