Shifting computing architectures from von Neumann to event-based spiking neural networks (SNNs) uncovers new opportunities for low-power processing of sensory data in applications such as vision or sensorimotor control. Exploring roads toward cognitive SNNs requires the design of compact, low-power and versatile experimentation platforms with the key requirement of online learning in order to adapt and learn new features in uncontrolled environments. However, embedding online learning in SNNs is currently hindered by high incurred complexity and area overheads. In this work, we present ODIN, a 0.086-mmμ 64k-synapse 256-neuron online-learning digital spiking neuromorphic processor in 28nm FDSOI CMOS achieving a minimum energy per synaptic operation (SOP) of 12.7pJ. It leverages an efficient implementation of the spike-driven synaptic plasticity (SDSP) learning rule for high-density embedded online learning with only 0.68μm2 per 4-bit synapse. Neurons can be independently configured as a standard leaky integrate-and-fire (LIF) model or as a custom phenomenological model that emulates the 20 Izhikevich behaviors found in biological spiking neurons. Using a single presentation of 6k 16×16 MNIST training images to a single-layer fully-connected 10-neuron network with on-chip SDSP-based learning, ODIN achieves a classification accuracy of 84.5% while consuming only 15nJ/inference at 0.55V using rank order coding. ODIN thus enables further developments toward cognitive neuromorphic devices for low-power, adaptive and low-cost processing.

Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip memory accesses, memory reduction requirements for weight storage pushed toward the use of binary weights, which were demonstrated to have a limited accuracy reduction on many applications when quantization-aware training techniques are used. In parallel, spiking neural network (SNN) architectures are explored to further reduce power when processing sparse event-based data streams, while on-chip spike-based online learning appears as a key feature for applications constrained in power and resources during the training phase. However, designing power- and area-efficient spiking neural networks still requires the development of specific techniques in order to leverage on-chip online learning on binary weights without compromising the synapse density. In this work, we demonstrate MorphIC, a quad-core binary-weight digital neuromorphic processor embedding a stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning rule and a hierarchical routing fabric for large-scale chip interconnection. The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF) neurons and more than two million plastic synapses for an active silicon area of $2.86 \text{mm}^2$ in 65nm CMOS, achieving a high density of 738k synapses/ $\text{mm}^2$ . MorphIC demonstrates an order-of-magnitude improvement in the area-accuracy tradeoff on the MNIST classification task compared to previously-proposed SNNs, while having no penalty in the energy-accuracy tradeoff.

While Moore’s law has driven exponential computing power expectations, its nearing end calls for new avenues for improving the overall system performance. One of these avenues is the exploration of alternative brain-inspired computing architectures that aim at achieving the flexibility and computational efficiency of biological neural processing systems. Within this context, neuromorphic engineering represents a paradigm shift in computing based on the implementation of spiking neural network architectures in which processing and memory are tightly colocated. In this article, we provide a comprehensive overview of the field, highlighting the different levels of granularity at which this paradigm shift is realized and comparing design approaches that focus on replicating natural intelligence (bottom-up) versus those that aim at solving practical artificial intelligence applications (top-down). First, we present the analog, mixed-signal, and digital circuit design styles, identifying the boundary between processing and memory through time multiplexing, in-memory computation, and novel devices. Then, we highlight the key tradeoffs for each of the bottom-up and top-down design approaches, survey their silicon implementations, and carry out detailed comparative analyses to extract design guidelines. Finally, we identify necessary synergies and missing elements required to achieve a competitive advantage for neuromorphic systems over conventional machine-learning accelerators in edge computing applications and outline the key ingredients for a framework toward neuromorphic intelligence.

Simultaneous wireless information and power transfer (SWIPT) is a flexible and cheap way to supply Internet-of-Things (IoT) smart sensors avoiding battery replacement. In this paper, we analyze, model, and design a 2.45-GHz RF energy harvesting (RFEH) system based on a discrete-component matching network (MN), a custom 65-nm CMOS cross-coupled rectifier, and an off-the-shelf storage-charging power management unit (PMU), which regulates the rectifier output voltage with maximum power point tracking (MPPT). We propose a reverse global analysis to model the RFEH. It allows an accurate prediction of the power harvesting efficiency (PHE) to directly size the MN and select the RFEH MPPT regulation ratio, at different incident RF power levels. We perform parasitic-aware RFEH design to take advantage of printed circuit board (PCB)/package capacitive parasitics at the rectifier input for optimizing the π-MN with the help of the proposed RFEH modeling results. We show that this parasitic capacitance introduces a maximum bound on the real impedance at the rectifier input to ensure good impedance matching in practice. MPPT is used to help reach this target real impedance at given incident RF power, as the rectifier equivalent input impedance is a function of both its input and output voltages. Measurement results show a sensitivity as low as -17.1 dBm with a peak PHE of 48.3% at -3-dBm incident RF power. Global modeling, simulation, and measurement results demonstrate that the PHE is limited by PCB/package parasitic capacitance and that PCB/packaging technology improvement to reduce parasitic capacitance by 150 fF could boost the PHE up to 45% for a low incident RF power level of -10 dBm.

Given the ubiquity of electronic devices and the urgent need to decrease our footprint in the context of global warming and planetary boundaries, it becomes critical to better quantify the environmental impacts of integrated circuit (IC) production. Our work addresses this question in three successive steps. First, we carry out a review of the data available since 2010 from four different literature categories, i.e., foundry reports, industry roadmaps, scientific literature, and life-cycle assessment databases. Then, we leverage the 27 identified sources to perform both a qualitative and quantitative analysis. We propose 10 features for characterizing the scope of studies while focusing on environmental indicators normalized per cm, i.e., energy consumption, carbon footprint and water consumption. The analysis results highlight a clear increasing trend of the environmental footprint with CMOS technology downscaling below 0.13 μm, despite a significant variation between the sources mainly due to scope mismatch. Finally, we show that environmental impacts per cm did not significantly decrease compared to historical values from 1980–2010, whereas the total silicon area produced keeps on increasing by 3.6%/year. Consequently, this work calls for urgently rethinking the road ahead with sobriety to effectively decrease the absolute environmental footprint of the IC production sub-sector.