Given the ubiquity of electronic devices and the urgent need to decrease our footprint in the context of global warming and planetary boundaries, it becomes critical to better quantify the environmental impacts of integrated circuit (IC) production. Our work addresses this question in three successive steps. First, we carry out a review of the data available since 2010 from four different literature categories, i.e., foundry reports, industry roadmaps, scientific literature, and life-cycle assessment databases. Then, we leverage the 27 identified sources to perform both a qualitative and quantitative analysis. We propose 10 features for characterizing the scope of studies while focusing on environmental indicators normalized per cm, i.e., energy consumption, carbon footprint and water consumption. The analysis results highlight a clear increasing trend of the environmental footprint with CMOS technology downscaling below 0.13 μm, despite a significant variation between the sources mainly due to scope mismatch. Finally, we show that environmental impacts per cm did not significantly decrease compared to historical values from 1980–2010, whereas the total silicon area produced keeps on increasing by 3.6%/year. Consequently, this work calls for urgently rethinking the road ahead with sobriety to effectively decrease the absolute environmental footprint of the IC production sub-sector.

Information and communication technologies are often considered by policymakers, industrial stakeholders and scientists as a key lever in the run towards sustainability, since they should ease energy efficiency and dematerialization. In this opinion article, nurtured by the inputs of a broad panel of experts, we challenge this widely spread view by highlighting the detrimental social and environmental footprints caused by digital technologies. We further take a critical look on the ways innovation is conducted nowadays, i.e., with an almost exclusive focus on performance and few considerations for externalities. This leads us to call for academic teaching programs advocating for a holistic approach, for new business models, and for ambitious political decisions able to drive a paradigm shift in the mainstream agenda of electronics innovation and digital transition that shall significantly contribute to the well-being of everyone, everywhere, without compromising future generations. We conclude that digital technologies cannot support long-term sustainability if their only purpose remains the optimization of the current system.

We present an ultra-thin lateral SOI PIN photodiode with transferred monolayer graphene as the transparent gate, to provide enhanced ultraviolet (UV) performance and mechanical flexibility beyond standard Si-based devices. The device dark current shows intact characteristics after the post-CMOS thinning and graphene transfer processing steps. The device responsivity presents high potential in UV and visible wavelength detections (i.e. within the 200–900 nm range) under monochromatic light illumination. A maximum responsivity of 0.18 A W ⁻¹ has been experimentally achieved at 390 nm wavelength and validated by simulation, for a diode with intrinsic length L _i of 20 μ m. Additionally, the ~5 μ m-thick device chip with direct board assembly paves the way towards the development of hybrid flexible electronics.

In this paper, we are presenting a new classification methodology for high resolution membrane based MEMS piezoresistive pressure sensors embedded in Internet of Things (IoT) nodes or in body-implanted devices. This is based on a new figure of merit (FoM) that includes the four key parameters as the power consumption, the area, the noise and the sensitivity of the transducer. The proposed classification allows to directly evaluate, based on power consumption and area requirements, the ultimate limit of detection that can be reached by a proposed technology. The derivation of the proposed FoM is validated based on wide survey and comparisons of literature results. It shows that, until now, wet etching technics for membrane release still allow for reaching higher performances than reactive ion etching.

This paper aims at comparing the tuning range of three different planar inductor layouts built on a Printed Circuit Boards (PCB), namely the spiral inductor, the nonspiral inductor, and the meander inductor. Initially, we identify the equivalent electric model for the three inductors. All models are validated theoretically by analytical equations, by simulation through Sonnet software ^® , and also by measurements. For the same surface occupancy, the spiral inductor presents the higher inductance value, while the nonspiral inductor has the higher quality factor and self-resonant frequency. The tunability range is investigated by placing a shielding metal plate above for all PCB inductors. The inductance value is reduced, when the air gap between the metal plate and the inductance decreases. In addition, results demonstrated that the spiral inductor has the higher range, with a variation of more than 90%, followed by the non-spiral inductor. The meander one showed a change less than one-tenth of the spiral inductor.