A neuromorphic system is composed of hardware-based artificial neurons and synaptic devices, designed to improve the efficiency of neural computations inspired by energy-efficient and parallel operations of the biological nervous system. A synaptic device-based array can compute vector–matrix multiplication (VMM) with given input voltage signals, as a non-volatile memory device stores the weight information of the neural network in the form of conductance or capacitance. However, unlike software-based neural networks, the neuromorphic system unavoidably exhibits non-ideal characteristics that can have an adverse impact on overall system performance. In this study, the characteristics required for synaptic devices and their importance are discussed, depending on the targeted application. We categorize synaptic devices into two types: conductance-based and capacitance-based, and thoroughly explore the operations and characteristics of each device. The array structure according to the device structure and the VMM operation mechanism of each structure are analyzed, including recent advances in array-level implementation of synaptic devices. Furthermore, we reviewed studies to minimize the effect of hardware non-idealities, which degrades the performance of hardware neural networks. These studies introduce techniques in hardware and signal engineering, as well as software-hardware co-optimization, to address these non-idealities through compensation approaches.

The progress of artificial intelligence and the development of large‐scale neural networks have significantly increased computational costs and energy consumption. To address these challenges, researchers are exploring low‐power neural network implementation approaches and neuromorphic computing systems are being highlighted as potential candidates. Specifically, the development of high‐density and reliable synaptic devices, which are the key elements of neuromorphic systems, is of particular interest. In this study, an 8 × 16 memcapacitor crossbar array that combines the technological maturity of flash cells with the advantages of NAND flash array structure is presented. The analog properties of the array with high reliability are experimentally demonstrated, and vector‐matrix multiplication with extremely low error is successfully performed. Additionally, with the capability of weight fine‐tuning characteristics, a spiking neural network for CIFAR‐10 classification via off‐chip learning at the wafer level is implemented. These experimental results demonstrate a high level of accuracy of 92.11%, with less than a 1.13% difference compared to software‐based neural networks (93.24%).

Memristor devices can be utilized for various computing applications, and stochastic computing is one of them. The intrinsic stochastic characteristics of the memristor cause unpredictable current fluctuations by the capture and emission of electrons in a trap site. Herein, a true random number generator (TRNG) using the random telegraph noise (RTN) of the memristor as an entropy source is proposed. TiO_x/Al₂O₃ memristors are fabricated, and the capture time probability of the RTN characteristics is modulated to 50% with varying read‐voltage and device conductance state. In addition, the TRNG operations with the RTN current signals as entropy sources are experimentally demonstrated with a customized breadboard, and the randomness is verified with the National Institute of Standards and Technology (NIST) tests.

Ferroelectric memories have undergone a transformative evolution from conventional perovskite-based materials to modern fluorite-structured ferroelectrics, driven by the pursuit of scalable, low-power, and CMOS-compatible non-volatile memory solutions. The observation of ferroelectricity in nanoscale HfO ₂ -based films has enabled integration with CMOS-compatible processes, providing advantages such as potential scalability, low power consumption, and non-volatility, while facilitating continued scaling and high-density integration. Leveraging established materials infrastructure in the semiconductor industry, hafnia–based ferroelectrics have been incorporated in various memory architectures, including ferroelectric random-access memory (FeRAM), ferroelectric tunnel junctions (FTJs), ferroelectric field-effect transistors (FeFETs), and ferroelectric memcapacitors (FeCAPs). Beyond conventional non-volatile storage, these devices have also emerged as promising building blocks for in-memory computing applications, including neuromorphic systems, hardware security primitives, and associative memory. In this review, we explore the historical development of ferroelectric memories from a materials–device co-design perspective, examine recent advances in device architectures and in-memory computing applications, and discuss the remaining challenges in endurance, retention, variability, and scaling. Finally, we propose future research directions that integrating material innovation, interface engineering, and circuit-level optimization to realize the full potential of ferroelectric memories in next-generation computing platforms. Graphical abstract

In this study, we experimentally validate a true random number generator (TRNG) utilizing a memcapacitor with TiN/Al ₂ O ₃ /HfO ₂ /SiO ₂ /Si (TAHOS) flash stack. The memcapacitor, incorporating a charge trapping layer, generates a displacement current via charge-discharge operations, and the current can be adjusted depending on the device state. Leveraging the randomness inherent in each switching cycle, this device can serve as an entropy source for the TRNG circuit. The generated bitstream has achieved a 95% confidence level in autocorrelation tests and has successfully passed 15 statistical tests from the National Institute of Standards and Technology (NIST), confirming its randomness and independence. This demonstrates the potential for stable and reliable hardware-based information security and encryption technology.