The superior density of passive analog-grade memristive crossbar circuits enables storing large neural network models directly on specialized neuromorphic chips to avoid costly off-chip communication. To ensure efficient use of such circuits in neuromorphic systems, memristor variations must be substantially lower than those of active memory devices. Here we report a 64 × 64 passive crossbar circuit with ~99% functional nonvolatile metal-oxide memristors. The fabrication technology is based on a foundry-compatible process with etch-down patterning and a low-temperature budget. The achieved <26% coefficient of variance in memristor switching voltages is sufficient for programming a 4K-pixel gray-scale pattern with a <4% relative tuning error on average. Analog properties are also successfully verified via experimental demonstration of a 64 × 10 vector-by-matrix multiplication with an average 1% relative conductance import accuracy to model the MNIST image classification by ex-situ trained single-layer perceptron, and modeling of a large-scale multilayer perceptron classifier based on more advanced conductance tuning algorithm.

We demonstrate the hardware implementation of spiking neural network (SNN) with synaptic transistors and neuron circuits. The method of conversion from software fully-connected network (FCN) to hardware SNN with little degradation is discussed. The degradation of classification accuracy is analyzed in terms of device variation and noisy images. In addition, the accuracy degradation is significantly improved by stacking denoising autoencoder (DAE) layer. FCN-SNN conversion with very little performance drop is demonstrated using weight normalization, and SNN with DAE layer shows a great tolerance to input image noise.

In the past few decades, NAND flash memory has been one of the most successful nonvolatile storage technologies, and it is commonly used in electronic devices because of its high scalability and reliable switching properties. To overcome the scaling limit of planar NAND flash arrays, various three-dimensional (3D) architectures of NAND flash memory and their process integration methods have been investigated in both industry and academia and adopted in commercial mass production. In this paper, 3D NAND flash technologies are reviewed in terms of their architecture and fabrication methods, and the advantages and disadvantages of the architectures are compared.

A neuromorphic system is composed of hardware-based artificial neurons and synaptic devices, designed to improve the efficiency of neural computations inspired by energy-efficient and parallel operations of the biological nervous system. A synaptic device-based array can compute vector–matrix multiplication (VMM) with given input voltage signals, as a non-volatile memory device stores the weight information of the neural network in the form of conductance or capacitance. However, unlike software-based neural networks, the neuromorphic system unavoidably exhibits non-ideal characteristics that can have an adverse impact on overall system performance. In this study, the characteristics required for synaptic devices and their importance are discussed, depending on the targeted application. We categorize synaptic devices into two types: conductance-based and capacitance-based, and thoroughly explore the operations and characteristics of each device. The array structure according to the device structure and the VMM operation mechanism of each structure are analyzed, including recent advances in array-level implementation of synaptic devices. Furthermore, we reviewed studies to minimize the effect of hardware non-idealities, which degrades the performance of hardware neural networks. These studies introduce techniques in hardware and signal engineering, as well as software-hardware co-optimization, to address these non-idealities through compensation approaches.

Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with two electrically independent gates to realize a hardware-based neural network system without any switching components. The spike-timing dependent plasticity characteristics of the synaptic devices are measured and analyzed. With the help of the device model based on the measured data, the pattern recognition capability of the hardware-based spiking neural network systems is demonstrated using the modified national institute of standards and technology handwritten dataset. By comparing systems with and without inhibitory synapse part, it is confirmed that the inhibitory synapse part is an essential element in obtaining effective and high pattern classification capability.

To apply resistive random‐access memory (RRAM) to the neuromorphic system and improve performance, each cell in the array should be able to operate independently by reducing device variation. In addition, it is necessary to lower the operating current of the RRAM cell and enable gradual switching characteristics to mimic the low‐energy operations of biological. In most filamentary RRAMs, however, overshoot current occurs in the forming stage, and the RRAM shows large device variation, high operating current, and abrupt set and reset switching characteristics. Herein, the shortcomings occurring in the forming stage are overcome by introducing and optimizing an overshoot suppression layer. Consequently, the RRAM exhibits gradual switching characteristics both in the set and reset regions, thereby enabling implementation of 4‐bit multilevel operation. In addition, the forming step can be easily performed in a 16 × 16 crossbar array owing to its self‐compliance characteristics without disturbing neighboring cells in the array. The tuning and vector–matrix multiplication (VMM) operations are also experimentally verified in the array. Finally, classification performance with off‐chip training is compared in terms of accuracy and robustness to tuning tolerance depending on the number of bits of the implemented multiconductance levels.