This article presents a dynamic range (DR) enhanced discrete-time delta–sigma modulator (DTDSM) applied to the Internet of Things (IoT). It is based on an asynchronous 1.5-bit successive-approximation-resister (SAR) quantizer and a tri-level feedback capacitive digital-to-analog converter (CDAC), eliminating the dynamic element matching (DEM) overhead. The proposed DR enhancement (DRE) technique based on a variable threshold ( $V_{\text {TH}}$ ) allows the system to achieve maximum benefits at different input amplitudes. The system is configured in a high loop gain mode at small input amplitudes, providing the system with a stronger noise-shaping (NS) capability. The system is configured in the maximum stable amplitude (MSA) mode for large input amplitudes. In addition, we modified the working model of the cascoded floating inverter amplifier (FIA) in the weak inversion region. The prototype DTDSM is implemented in a 180-nm CMOS process, achieving a 94.7-dB DR and 92.4-dB signal-to-noise-and-distortion ratio (SNDR) at a 700-Hz bandwidth with only 2.3- $\mu \text{W}$ power consumption. As a result, the Schreier figure-of-merit (FoM) for SNDR and DR is 177.2 and 179.5 dB, respectively.

A voltage reference is indispensable in Integrated Circuits. To improve the limited linear output voltage range and energy efficiency of a voltage reference, we innovatively propose a switched-capacitor-based programmable voltage reference scheme employing inverter-based OTAs to reduce the power consumption, simultaneously using a novel Correlated Level Shifting (CLS) technique (without active overhead) to enhance the OTA’s DC gain and integral gain. Experimented with SMIC 180 nm CMOS technology, a scheme-based voltage reference realizes a programable output voltage range from 266 to 995 mV at −30 to 120 °C, and the corresponding temperature coefficient (TC) ranges from 82.4 to 99.5 ppm/°C. The power consumption is 976 nW. Furthermore, comparative experiments and evaluations with other schemes have unequivocally verified the superiority of our proposed scheme, characterized by its high energy efficiency and wide output voltage range. The scheme can be suitably deployed in a multitude of novel edge-data processing systems.

This paper presents a low-power, high-gain integrator design that uses a cascode operational transconductance amplifier (OTA) with floating inverter–amplifier (FIA) assistance. Compared to a traditional cascode, the proposed integrator can achieve a gain of 80 dB, while reducing power consumption by 30%. Upon completing the analysis, the value of the FIA drive capacitor and clock scheme for the FIA-assisted OTA were obtained. To enhance the dynamic range (DR) and mitigate quantization noise, a tri-level quantizer was employed. The design of the feedback digital-to-analog converter (DAC) was simplified, as it does not use additional mismatch shaping techniques. A third-order, discrete-time delta–sigma modulator was designed and fabricated in a 0.18 μm complementary metal-oxide semiconductor (CMOS) process. It operated on a 1.8 V supply, consuming 221 µW with a 24 kHz bandwidth. The measured SNDR and DR were 90.9 dB and 95.3 dB, respectively.