The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.

In many sensor applications, a high-resolution analog-to-digital converter (ADC) is a key block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such applications. While the energy-efficiency of IADCs has improved by several orders of magnitude over the past decade, the implementation of high performance IADCs, especially in battery-powered systems, is still challenging. This paper presents a tutorial review on energy-efficient IADCs and addresses the progress in this area. This paper describes the fundamentals of IADCs and energy-efficient hybrid IADC architectures. Various design techniques for improving the energy-efficiency of the IADCs are described. This paper is intended to serve as a starting point for the development of a new energy-efficient IADC.

An ultra-low quiescent current tri-mode DC-DC buck converter is presented in this paper, which is able to handle a 100,000X load range. In pulse width modulation (PWM) and pulse frequency modulation (PFM) mode, adaptive on-time (AOT) V² control is utilized to achieve seamless mode transition and constant switching frequency in PWM mode. A deep green mode (DGM) is proposed for light load, where both the switching loss and the power of control circuitry are minimized. By reducing the comparator current, a delay-based hysteresis window adaptive to load current is generated, reducing the switching frequency and the loss. Meanwhile, the average current of zero current detector (ZCD) and AOT controller are reduced significantly by dynamic biasing. As a result, the efficiency of the converter is improved while maintaining a reasonable output ripple. The proposed converter is implemented in a $0.18\mu $ m BCD technology. Experimental results show that the converter can provide a 1.6 V output from a 2.7 to 4.7V input for $1\mu $ A to 100 mA load, while consuming only 490nA quiescent current. The proposed converter achieves a 92.1% peak efficiency and efficiency can be maintained above 80% in a load range of $20\mu $ A to 60 mA.

This work presents a 48-1V dc–dc converter with an on-chip switch and gallium nitride (GaN) hybrid power conversion. By series connecting a 12-level Dickson switched-capacitor with a two-phase switched-inductor circuit, the capacitors take over most of the 48-V voltage stresses. The circuit, thus, reduces to an equivalent 4-1V converter, making the on-chip 5-V transistor applicable for a 48-V high-voltage design. Due to the easy integration of on-chip switches and superior switch figures of merit over other 48-1V counterparts, this proposed design is able to achieve the highest switching frequency, the lowest external switch count, and the improved power density compared with other prior-state-of-the-arts. The prototype was fabricated using a 0.18- $\mu \text{m}$ BCD process with an evaluation board volume of 17 mm $\times $ 15 mm $\times $ 2.6 mm. The converter achieves a maximum 8-A loading capacity with the input range from 36 to 60 V and the output from 0.5 to 1 V. The measured peak power efficiency is 90.2%, and the power density is 998 A/in ³ considering the power stage volume.

This article presents a 148-nW always-on wake-up system that drastically reduces the system power consumption of Internet of Things (IoT) sensor nodes while oftentimes operating in random-sparse-event (RSE) scenarios. To significantly reduce the long-term average (LTA) power consumption and realize multiapplication and intelligent event detection, three techniques are proposed: 1) In a three-stage pipelined event-driven architecture, a frame generator and a convolutional neural network intelligent inference engine (CNN IIE) in stage III are event-driven by the preliminary detectors in stage II, and the detectors are triggered by a level-crossing (LC) analog-to-digital converter (ADC), i.e., stage I, dramatically reducing the overall power consumption. 2) The clock-free pulse-based instant rate of change (IROC) feature extractor directly processes the asynchronous pulses of the LC-ADC outputs in the temporal domain instead of utilizing a conventional power-hungry frequency-domain method. 3) A reconfigurable IROC, the frame generator, and the CNN IIE provide adaptive intelligence for various IoT events, enhancing the accuracy of multipurpose detection with ultralow power. We demonstrate two artificial intelligence IoT (AIoT) applications at 0.6-V V _DD . For electrocardiogram (ECG) recognition, one example works at a typical event rate (ER) of ~4800/h, with an active power of 1.68 $\mu \text{W}$ and a precision of up to 99%; the other is used for keyword spotting (KWS), where the chip achieves 378 nW at ~720/h ER and 94% accuracy. The LTA power is bounded to 148 nW, while the event-driven chip is on call and waiting for events; this chip dominates the AIoT device battery life in RSE scenarios.

This work presents an ultra-low-power software-defined always-on wake-up system to drastically decrease the system power of Internet of Things (IoTs) devices, which usually operate in random-sparse-event (RSE) scenarios. It mainly thanks to a clock-free time-shielding level-crossing ADC (TS-LCADC), software-defined clock-free multi-function detectors, and an asynchronous pipelined event-driven architecture. First, by quantifying RSE noisy signals with clock-free adaptive sampling in a signal-noise-rejecting manner, the proposed TS-LCADC reduces number of sampling points and power, and consumes only 41 nW when on-call waiting for IoT events. Second, the proposed clock-free multi-function detectors with offline and online programmability are able to character the signal features of versatile IoTs events and allow versatile and dynamic wake-up functions. Third, the proposed asynchronous pipelined event-driven architecture minimizes the system activity and thus power, because a power-hungry high-performance system (HPS) is only woken up when a detected parameter crosses its corresponding threshold. As such, the long-term average power (LTA-power) is dominated by the always-on circuits in RSE scenarios. The measurement results achieve 71–75 nW for three typical applications, i.e., heart rate, epilepsy, and keyword envelope detection. The LTA power is only 57 nW when waiting for RSE events, which is 30 $\times $ lower than a prior general-purpose wake-up chip. Compared with other works of dedicated voice and acoustic wake-up functions, this work consumes 2 $\times $ and 17 $\times $ less power, respectively, while featuring 16 $\times $ higher signal bandwidth and a broader versatility.