SiC MOSFETs (silicon carbide metal‐oxide semiconductor field‐effect transistors) are replacing Si insulated gate bipolar transistors in many power conversion applications due to their superior performance. However, ruggedness and reliability of SiC MOSFETs are still big concern for their widespread applications in the market, especially in safety‐critical applications. The objective of this study is to provide a comprehensive picture on the ruggedness and reliability of commercial SiC MOSFETs, discover their failure or degradation mechanism, and propose some possible mitigation methods through both literature survey and in‐depth analysis. The ruggedness of SiC MOSFETs discussed here includes short‐circuit (SC) ruggedness, avalanche ruggedness, and their failure mechanism. The reliability issues include gate oxide reliability, degradation under high‐temperature bias stress, repetitive SC stress, avalanche stress, power cycling stress, body diode's surge current stress, and their degradation mechanism. Furthermore, this study discusses methods and solutions to improve their ruggedness and reliability.

Online junction temperature monitoring of power devices is a viable technique to ensure the reliable operation of mission-critical power electronic converters. This paper provides a potential approach for junction temperature estimation of SiC MOSFETs based on the dynamic threshold voltage. The proposed method is independent of load current variation, which eliminates the complicated calibration procedure with the load current. First, the physical mechanism and the temperature dependence of dynamic threshold voltage are analyzed. An analytical model for the dynamic threshold voltage is built to investigate the effects of gate loop parameters on the temperature sensitivity and measurement accuracy. Then, the principle of dynamic threshold voltage measurement circuit is introduced. Finally, the proposed dynamic threshold voltage measurement circuit is experimentally evaluated through the double pulse tests. Experimental results show that the dynamic threshold voltage of SiC MOSFET has a good linear relationship with junction temperature. The temperature sensitivity of dynamic threshold voltage of two SiC MOSFETs is approximately 5.2mV/°C and 19.6 mV/°C, respectively.

The hybrid switch concept of paralleling a higher-current main Si IGBT and a lower-current auxiliary SiC MOSFET offers an improved cost/performance tradeoff in power converters.Currently the gate control strategy of these two internal devices emphasizes on minimizing the total power loss,and is referred to as the efficiency control mode.However, there is a serious risk of overheating and reliability degradation of the SiC MOSFET if solely relying on this control strategy.In this paper,we propose a new method of gate control optimization,referred to as the thermal balance control mode,to keep the junction temperature of both devices within the specified temperature range,and to minimize the total power loss simultaneously.We first investigate the dependency of the hybrid switch's switching losses on the gate control pattern.We then extensively study control optimization in these two distinct control modes in a DC/DC boost converter.It is found that the thermal balance control mode can achieve almost the same total power loss as the efficiency control mode,but much lower and more balanced junction temperatures of the two internal devices.Experimental results demonstrate that the Si/SiC hybrid switch in an optimal thermal balance control mode can achieve a 163% higher power handling capability and four times higher switching frequency than a single IGBT solution.

The hybrid switch (HyS) of a higher-current main Si IGBT and a parallel lower-current auxiliary Silicon Carbide (SiC) mosfet offer an improved cost/performance tradeoff for practical power electronic designs. The purpose of this paper is to investigate the short-circuit (SC) ruggedness, failure mechanisms, and techniques for improvement of the Silicon/SiC HyS. The influence of major limiting factors, including dc bus voltage, gate drive voltage, gate control pattern, case temperature, and SiC mosfet sizing are experimentally studied. Two SC failure mechanisms, the thermal runaway and gate interlayer dielectric breakdown of the SiC mosfet are identified using microscopic failure analysis techniques. An optimum gate control selection is proposed to improve the HyS's SC withstanding time with minimum increase in its power loss.

The reliability concern of SiC MOSFETs has been extensively investigated with various accelerated stress tests. However, these conventional tests are predominantly performed in a simplified and controlled testing environment, which might or might not realistically simulate the actual device operation profiles in power converters. In this paper, we report the long-term degradation phenomenon of several types of SiC MOSFETs in an actual 2kW Power Factor Correction (PFC) converter and provide an analysis of the degradation mechanisms. Compared to conventional DC power cycling tests, a large decrease in threshold voltage was observed due to gate oxide degradation of SiC MOSFET in the PFC converter. Online monitoring results show that the on-state voltage drop of SiC MOSFET continuously rises with the increase of stress times. The increase in on-state voltage is caused by the change of package resistance and channel resistance. Gate oxide degradation resulting in a large increase in drain-source leakage current and gate leakage current. Meanwhile, the variation of miller plateau voltage and threshold voltage results in a significant change of turn-on losses in SiC MOSFET. TCAD simulation and C-V measurement indicate that the main degradation mechanism is hot holes accumulate within the gate oxide above the JFET region and channel region due to high electric field stress.