There has been an increasing interest in using model predictive control (MPC) for power electronic applications. However, the exponential increase in computational complexity and demand of computing resources hinders the practical adoption of this highly promising control technique. In this article, a new MPC approach using an artificial neural network (termed ANN-MPC) is proposed to overcome these barriers. A power converter with a virtual MPC controller is first designed and operated under a circuit simulation or power hardware-in-the-loop simulation environment. An artificial neural network (ANN) is then trained offline with the input and output data of the virtual MPC controller. Next, an actual FPGA-based MPC controller is designed using the trained ANN instead of relying on heavy-duty mathematical computation to control the actual operation of the power converter in real time. The ANN-MPC approach can significantly reduce the computing need and allow the use of more accurate high-order system models due to the simple mathematical expression of ANN. Furthermore, the ANN-MPC approach can retain the robustness for system parameter uncertainties by flexibly setting the input elements. The basic concept, ANN structure, offline training method, and online operation of ANN-MPC are described in detail. The computing resource requirement of the ANN-MPC and conventional MPC are analyzed and compared. The ANN-MPC concept is validated by both simulation and experimental results on two kW-class flying capacitor multilevel converters. It is demonstrated that the FPGA-based ANN-MPC controller can significantly reduce the FPGA resource requirement (e.g., 2.11 times fewer slice LUTs and 2.06 times fewer DSPs) while offering a control performance same as the conventional MPC.

SiC MOSFETs (silicon carbide metal‐oxide semiconductor field‐effect transistors) are replacing Si insulated gate bipolar transistors in many power conversion applications due to their superior performance. However, ruggedness and reliability of SiC MOSFETs are still big concern for their widespread applications in the market, especially in safety‐critical applications. The objective of this study is to provide a comprehensive picture on the ruggedness and reliability of commercial SiC MOSFETs, discover their failure or degradation mechanism, and propose some possible mitigation methods through both literature survey and in‐depth analysis. The ruggedness of SiC MOSFETs discussed here includes short‐circuit (SC) ruggedness, avalanche ruggedness, and their failure mechanism. The reliability issues include gate oxide reliability, degradation under high‐temperature bias stress, repetitive SC stress, avalanche stress, power cycling stress, body diode's surge current stress, and their degradation mechanism. Furthermore, this study discusses methods and solutions to improve their ruggedness and reliability.

Online junction temperature monitoring of power devices is a viable technique to ensure the reliable operation of mission-critical power electronic converters. This paper provides a potential approach for junction temperature estimation of SiC MOSFETs based on the dynamic threshold voltage. The proposed method is independent of load current variation, which eliminates the complicated calibration procedure with the load current. First, the physical mechanism and the temperature dependence of dynamic threshold voltage are analyzed. An analytical model for the dynamic threshold voltage is built to investigate the effects of gate loop parameters on the temperature sensitivity and measurement accuracy. Then, the principle of dynamic threshold voltage measurement circuit is introduced. Finally, the proposed dynamic threshold voltage measurement circuit is experimentally evaluated through the double pulse tests. Experimental results show that the dynamic threshold voltage of SiC MOSFET has a good linear relationship with junction temperature. The temperature sensitivity of dynamic threshold voltage of two SiC MOSFETs is approximately 5.2mV/°C and 19.6 mV/°C, respectively.

The hybrid switch concept of paralleling a higher-current main Si IGBT and a lower-current auxiliary SiC MOSFET offers an improved cost/performance tradeoff in power converters.Currently the gate control strategy of these two internal devices emphasizes on minimizing the total power loss,and is referred to as the efficiency control mode.However, there is a serious risk of overheating and reliability degradation of the SiC MOSFET if solely relying on this control strategy.In this paper,we propose a new method of gate control optimization,referred to as the thermal balance control mode,to keep the junction temperature of both devices within the specified temperature range,and to minimize the total power loss simultaneously.We first investigate the dependency of the hybrid switch's switching losses on the gate control pattern.We then extensively study control optimization in these two distinct control modes in a DC/DC boost converter.It is found that the thermal balance control mode can achieve almost the same total power loss as the efficiency control mode,but much lower and more balanced junction temperatures of the two internal devices.Experimental results demonstrate that the Si/SiC hybrid switch in an optimal thermal balance control mode can achieve a 163% higher power handling capability and four times higher switching frequency than a single IGBT solution.

The optimal gate delay time control between the two internal devices to achieve the excellent electrical and thermal performance of the Si/SiC hybrid switch is considerably affected by several factors and requires careful adjustment to suit the different operation conditions of power converters. However, the conventional gate control solution for the hybrid switch applies a fixed delay time to achieve the minimum switching loss at a specific load current, resulting in disparities in junction temperature of internal devices over a wide load range. This effectively reduced the safe operating area by risking one internal switch subjected to overrated junction temperature in a wide range operation with regard to power handling condition. To avoid such a serious risk of reliability degradation or thermal breakdown, a novel active gate delay time control strategy based on the electro-thermal coupling loss model is proposed. The gate delay time was dynamically adjusted and optimized according to the operation conditions of power converters so that the operation junction temperature difference of the two internal devices can be minimized. Experimental results demonstrate that the junction temperature of the hybrid switch decreases by 20°C at 8kW load condition and its maximum power handling capability increases by 18% without compromising the power converter's efficiency in a 20 kHz Si/SiC hybrid switch based DC/DC buck converter compared with the conventional approach.