Online junction temperature monitoring of power devices is a viable technique to ensure the reliable operation of mission-critical power electronic converters. This paper provides a potential approach for junction temperature estimation of SiC MOSFETs based on the dynamic threshold voltage. The proposed method is independent of load current variation, which eliminates the complicated calibration procedure with the load current. First, the physical mechanism and the temperature dependence of dynamic threshold voltage are analyzed. An analytical model for the dynamic threshold voltage is built to investigate the effects of gate loop parameters on the temperature sensitivity and measurement accuracy. Then, the principle of dynamic threshold voltage measurement circuit is introduced. Finally, the proposed dynamic threshold voltage measurement circuit is experimentally evaluated through the double pulse tests. Experimental results show that the dynamic threshold voltage of SiC MOSFET has a good linear relationship with junction temperature. The temperature sensitivity of dynamic threshold voltage of two SiC MOSFETs is approximately 5.2mV/°C and 19.6 mV/°C, respectively.

It is highly desirable to monolithically integrate a high-performance freewheeling diode (FWD) in both Si and SiC power MOSFETs for power electronic applications. This is especially true for a SiC MOSFET since its inherent body diode has a very large turn-on knee voltage (~2.7 V). The purpose of this numerical study is to investigate a new 1200 V SiC MOSFET structure with an integrated heterojunction diode formed between n-type polysilicon and n-type SiC (termed HJD-MOSFET). The proposed HJD-MOSFET uses a mesa structure to accommodate the heterojunction FWD without sacrificing any active area while leaving the split-gate planar MOSFET cells in the trench. A p-shield region surrounding the heterojunction, along with the p-base of the MOS cells, shields high electric fields and maintains a high breakdown voltage. Three key HJD-MOSFET device parameters are identified and optimized in this article. The HJD-MOSFET offers a turn-on knee voltage of 0.5 V, roughly five times lower than the intrinsic SiC body diode or two times lower than a typical SiC Schottky barrier diode due to the low barrier height of the n/n heterojunction (~0.68 eV). Finally, the gate charge of HJD-MOSFET is reduced by 42% compared with conventional MOSFET since the poly-Si gate electrode is significantly reduced to accommodate the heterojunction FWD.

The reliability concern of SiC MOSFETs has been extensively investigated with various accelerated stress tests. However, these conventional tests are predominantly performed in a simplified and controlled testing environment, which might or might not realistically simulate the actual device operation profiles in power converters. In this paper, we report the long-term degradation phenomenon of several types of SiC MOSFETs in an actual 2kW Power Factor Correction (PFC) converter and provide an analysis of the degradation mechanisms. Compared to conventional DC power cycling tests, a large decrease in threshold voltage was observed due to gate oxide degradation of SiC MOSFET in the PFC converter. Online monitoring results show that the on-state voltage drop of SiC MOSFET continuously rises with the increase of stress times. The increase in on-state voltage is caused by the change of package resistance and channel resistance. Gate oxide degradation resulting in a large increase in drain-source leakage current and gate leakage current. Meanwhile, the variation of miller plateau voltage and threshold voltage results in a significant change of turn-on losses in SiC MOSFET. TCAD simulation and C-V measurement indicate that the main degradation mechanism is hot holes accumulate within the gate oxide above the JFET region and channel region due to high electric field stress.

In this article, we proposed a comprehensive model for predicting the degradation of SiC MOSFETs after gamma-ray irradiation. It is experimentally founded that SiC MOSFETs exhibit different degradation behaviors under gate bias (i.e., ${V}_{\text {GS}} =15$ V and ${V}_{\text {DS}} $ = 0 V) and drain bias (i.e., ${V}_{\text {GS}} $ = 0 V and ${V}_{\text {DS}} =400$ V) in terms of threshold voltage ( ${V}_{\text {TH}}$ ) and ON-resistance ( ${R}_{\text {ds}, \text{ON}}$ ). TCAD simulation shows that gate bias causes a high electric field in gate oxide above the MOS channel region, while drain bias generates relatively lower electric field in gate oxide around near-channel region. The differences in electric field under gate bias and drain bias lead to different hole yields and charge accumulation in gate oxide, which is the underlying physical mechanism for their different degradation behaviors. ${V}_{\text {TH}}$ is chosen as the parameter to quantify the accumulated charges in gate oxide and further predict irradiation-induced degradation. The relationship between the variation of threshold voltage ( ${\Delta} {V}_{\text {TH}}$ ) and the total ionizing doses (TIDs) under both gate and drain bias is formulated and validated. Comparison among measured data, TCAD simulation, and model prediction shows that the maximum prediction error is lower than 0.08 V, which proves the rationale and accuracy of the proposed degradation model. In addition, the two submodels for gate bias and drain bias are unified as one according to the time dependence effect (TDE) for TID irradiation. The proposed model could be useful to predict the degradation and/or lifetime of SiC MOSFETs in irradiation environments.

Monolithic integration of junction barrier-controlled Schottky (JBS) diode with SiC MOSFET (termed JMOS) offers unique advantages. However, the short-circuit (SC) ruggedness issue stands in the way of the development of the conventional JMOS. The purpose of this numerical study is to investigate a new 4H-SiC JMOS with a self-pinching (SP) structure formed in the JFET region (termed SP-JMOS). The SP structure features that an N-type current spread layer is sandwiched between the P+ layer and the buried P-shield layer, forming a lateral JFET channel. In the forward conduction state, the lateral JFET channel self-pinches off and clamps the potential, thus limiting the saturation current of the device. In the blocking state, both the P+ layer and the buried P-shield layer collaboratively shield the Schottky contact and the SiC/SiO ₂ interface from a high electric field for long-term reliable operation. Numerical simulation results show that the proposed SP-JMOS not only withstands a roughly $2.6\times $ longer SC withstanding time than that of the conventional JMOS, but also shows an ultralow oxide electric field in the SP-JMOS.

The 1.2-kV-rated 4H-SiC planar split-gate (SG) MOSFET embedding source field plate incorporated between separated gates (termed SFP-SG-MOSFET) is proposed and demonstrated. The utilization of the embedding source field plate in conventional SG-MOSFET (Conv-SG-MOSFETs) serves to alleviate the adverse effects of electric field crowding. It also maintains the minimum reverse transfer capacitance ( $\textit{C}_{\text{rss}}\text{)}$ . As a result, the high-frequency figure-of-merit (HF-FOM) and switching efficiency of the proposed SFP-SG MOSFET are improved compared to those of a conventional planar-gate MOSFET (Conv-PG-MOSFET) while maintaining the same blocking voltage rating. The experimental results demonstrate that $\textit{C}_{\text{rss}}$ of the fabricated devices is reduced by 80% and 53% at $\textit{V}_{\text{ds}}$ $=$ 0 V and $\textit{V}_{\text{ds}}$ $=$ 800 V, respectively. Thus, the SFP-SG-MOSFET exhibits HF-FOMs $<$ $\textit{R}_{\text{ON}}$ $\times$ $\textit{C}_{\text{rss}}$ $>$ 4.9 times lower at $\textit{V}_{\text{ds}}$ $=$ 0 V and 2.0 times lower at $\textit{V}_{\text{ds}}$ $=$ 800 V. Furthermore, the switching loss of the SFP-SG-MOSFET is reduced by 25%. This makes it possible for the proposed devices to handle a higher power density.