João Soares Navarro

Dr. João Soares Navarro


Research Focus & Metrics

Academic Career Length

6Years (2021-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

View All Publications
8 February 2024 in Electronics
Verified
Journal Article
Open access
PDF file
RGRodrigo Gounella
Rodrigo Gounella
GFGabriel Malheiro Ferreira
Gabriel Malheiro Ferreira
MAMarcio Amorim
Marcio Amorim
JNJoão Soares Navarro
João Soares Navarro
Joao CarmoJoao Carmo
Joao Carmo
This paper presents an overview of silicon-based optical sensors for the measurement of light in the visible spectrum range. The review is focused on sensors based on CMOS (complementary metal-oxide semiconductor) technology due to the high availability, low cost, ease of prototyping, and well-established fabrication processes. CMOS technology allows integration with the CMOS readout and control electronics in the same microdevice, featuring high-volume fabrication with high-reproducibility and low-cost. This review starts with an explanation of the phenomena behind opto-electronic transduction. It also presents and describes the most common components responsible for optical transduction, readout electronics, and their main characteristics. This review finishes with the presentation of selected applications to grasp where and how these sensors can be used.

17 March 2022 in Electronics
Verified
Journal Article
Open access
PDF file
TNTiago Matheus Nordi
Tiago Matheus Nordi
RGRodrigo Gounella
Rodrigo Gounella
MLMaximiliam Luppe
Maximiliam Luppe
JNJoão Soares Navarro
João Soares Navarro
EFErich Fonoff
Erich Fonoff
Joao CarmoJoao Carmo
Joao Carmo
Deep-brain stimulation (DBS) is an emerging research topic aiming to improve the quality of life of patients with brain diseases, and a great deal of effort has been focused on the development of implantable devices. This paper presents a low-noise amplifier (LNA) for the acquisition of biopotentials on DBS. This electronic module was designed in a low-voltage/low-power CMOS process, targeting implantable applications. The measurement results showed a gain of 38.6 dB and a −3 dB bandwidth of 2.3 kHz. The measurements also showed a power consumption of 2.8 μW. Simulations showed an input-referred noise of 6.2 μVRMS. The LNA occupies a microdevice area of 122 μm × 283 μm, supporting its application in implanted systems.

2 January 2021 in Analog Integrated Circuits and Signal Processing
Verified
Journal Article
Open access
PDF file
ACArthur Lombardi Campos
Arthur Lombardi Campos
JNJoão Soares Navarro
João Soares Navarro
MLMaximiliam Luppe
Maximiliam Luppe
ELEduardo Rodrigues de Lima
Eduardo Rodrigues de Lima
During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. The occupied area of the implemented ADC is 0.074 mm2.

TNTiago Matheus Nordi
Tiago Matheus Nordi
RGRodrigo Gounella
Rodrigo Gounella
MAMarcio Amorim
Marcio Amorim
MLMaximiliam Luppe
Maximiliam Luppe
JNJoão Soares Navarro
João Soares Navarro
Joao CarmoJoao Carmo
Joao Carmo
Deep-brain stimulation (DBS) is a highly effective and safe medical treatment that improves the lives of patients with a wide range of neurological and psychiatric diseases. It has been established as a first-line tool in the treatment of these conditions for the past two decades. Closed-loop deep-brain stimulation (CLDBS) advances this tool further by automatically adjusting the stimulation parameters in real time based on the brain’s response. In this context, this paper presents a low-noise amplifier (LNA) and a neurostimulator circuit fabricated using the low-power/low-voltage 65 nm CMOS process from TSMC. The circuits are specifically designed for implantable applications. To achieve the best tradeoff between input-referred noise and power consumption, metaheuristic algorithms were employed to determine and optimize the dimensions of the LNA devices during the design phase. Measurement results showed that the LNA had a gain of 41.2 dB; a 3 dB bandwidth spanning over three decades, from 1.5 Hz to 11.5 kHz; a power consumption of 5.9 µW; and an input-referred noise of 3.45 µVRMS, from 200 Hz to 11.5 kHz. The neurostimulator circuit is a programmable Howland current pump. Measurements have shown its capability to generate currents with arbitrary shapes and ranging from −325 µA to +318 µA. Simulations indicated a quiescent power consumption of 0.13 µW, with zero neurostimulation current. Both the LNA and the neurostimulator circuits are supplied with a 1.2 V voltage and occupy a microdevice area of 145 µm × 311 µm and 88 µm × 89 µm, respectively, making them suitable for implantation in applications involving closed-loop deep-brain stimulation.

17 May 2023 in Preprints.org
Verified
Preprint
Open access
PDF file
TNTiago Matheus Nordi
Tiago Matheus Nordi
RGRodrigo Gounella
Rodrigo Gounella
GGGabriel Ginja
Gabriel Ginja
MAMarcio Amorim
Marcio Amorim
MLMaximiliam Luppe
Maximiliam Luppe
Joao CarmoJoao Carmo
Joao Carmo
Deep-Brain Stimulation (DBS) is a a highly effective and safe medical treatment that improves the lives of patients with a wide range of neurological and psychiatric deceases, and has been consolidated as a first-line tool in the treatment of these conditionsin the last two decades. Closed Loop Deep-Brain Stimulation (CLDBS) pushes this tool further by automatically adjusting the stimulation parameters to the brain response in real time. In this context, this paper presents a Low-Noise Amplifier (LNA) and a Neurostimulator circuits fabricated in the low-power/low-voltage 65 nm CMOS process from the TSMC, which were designed targeting implantable applications. To achieve the best trade-off between input-referred noise and power consuption, metaheuristic algorithms were employed to determine and optimizes the dimentions of the LNA devices during the design phase. The measurement results showed that the LNA had a gain of 40.6 dB, a 3 dB bandwidth spanning over three decades from 10 Hz to 8.6 kHz, and a power consumption of 6.19 uW. Simulations results indicated an input-referred noise of 4.86 uVrms for the LNA. The circuit of the Neurostimulator is a programmable Howland Current-Pump, whose measurements showed its ability to generate currents with arbitrary shapes ranging from between 325 uA to +318 uA. The simulations showed a quiescent power consumption of 0.13 W with a zero neurostimulation current. The LNA and the Neurostimulator circuits are supplied with 1.2 V voltage and occupy a microdevice area of 145 um x 311 um and 88 um x 89 um, respectively, making them suitable for implantation in applications involving Closed Loop Deep-Brain Stimulation.