Digital true-random number generators (TRNG) are increasingly employed to generate random channels in low-power resource-constrained IoT devices at the network edge. However, their susceptibility to process variations, or even intrusion attacks, degrade the generated entropy requiring an on-the-fly processor for detection of bias variations and correction. This work proposes a two-step search process to implement an optimized search that minimizes the latency (number of clock-cycles) for bias correction implemented on a FPGA platform. The first step implements a subset of NIST tests for entropy validation and an additional autocorrelator is used for entropy validation and bias detection on-the-fly in the second step. Measured results with the proposed algorithm implemented on FPGA shows significant improvement in the probability of bias correction with low number of trials. The measured power consumption of the TRNG and the bias correction is 10.22mW and 10.96mW respectively at 1.25 V with 18 kHz throughput for three random channels.

The fractal dimension (FD) is an important feature used for classification and shape recognition. The best method to obtain the FD is the Bouligand‐Minkowski method. However, this method is computationally exhaustive because of the use of the distance transform. Presented is a modification in the method and a proposed architecture, suitable for field programmable gate array implementation that enables calculating the FD in a simple and efficient way.

Deep-brain stimulation (DBS) is an emerging research topic aiming to improve the quality of life of patients with brain diseases, and a great deal of effort has been focused on the development of implantable devices. This paper presents a low-noise amplifier (LNA) for the acquisition of biopotentials on DBS. This electronic module was designed in a low-voltage/low-power CMOS process, targeting implantable applications. The measurement results showed a gain of 38.6 dB and a −3 dB bandwidth of 2.3 kHz. The measurements also showed a power consumption of 2.8 μW. Simulations showed an input-referred noise of 6.2 μV_RMS. The LNA occupies a microdevice area of 122 μm × 283 μm, supporting its application in implanted systems.

The growth of digital communications has driven the development of numerous cryptographic methods for secure data transfer and storage. The SHA-256 algorithm is a cryptographic hash function widely used for validating data authenticity, identity, and integrity. The inherent SHA-256 computational overhead has motivated the search for more efficient hardware solutions, such as application-specific integrated circuits (ASICs). This work presents a custom ASIC hardware accelerator for the SHA-256 algorithm entirely created using open-source electronic design automation tools. The integrated circuit was synthesized using SkyWater SKY130 130 nm process technology through the OpenLANE automated workflow. The proposed final design is compatible with 32-bit microcontrollers, has a total area of 104,585 µm², and operates at a maximum clock frequency of 97.9 MHz. Several optimization configurations were tested and analyzed during the synthesis phase to enhance the performance of the final design.

During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. The occupied area of the implemented ADC is 0.074 mm².

In this paper we describe an approach to detect weed regions in sugarcane crops using Mask Regions with Convolutional Neural Networks (Mask R-CNN) on aerial images. Experiments were held with twelve combinations using ResNet-50 and ResNet-101 as backbones. We used both "trained from scratch" and transfer-learning from pre-trained datasets combined with image augmentation techniques for training. The ResNet-101 model with pre-trained COCO achieved an Average Precision (AP 50 ) of 65.5% and obtained values of 0.803, 0.707 and 0.752 for Precision, Recall and F 1 score. These results suggest a potential use of Mask R-CNN for weed mapping using aerial images.