In this letter, the ultrafast reverse recovery β -Ga ₂ O ₃ Schottky barrier diode (SBD) with improved breakdown voltage is proposed and investigated experimentally. It features the compound termination, consisting of air space field plate and thermal oxidation terminal. The compound termination not only reduces high-density interface states at the dielectric/Ga ₂ O ₃ interface and the electron concentration in the oxidation terminal, but also modulates the electric-field distribution and suppresses the peak electric-field at the bottom of anode. Therefore, the reverse leakage current is suppressed as well as the reverse recovery and breakdown characteristics are improved effectively. The Ga ₂ O ₃ SBDs with the diameter of 1000 μm obtain ultrashort reverse recovery time of 7.5 ns and ultralow reverse recovery charge of 1.0 nC at di / dt = 50 A/μs with its breakdown voltage up to 400 V, maintaining good rectification characteristics. The temperature-dependences of both forward conduction and reverse recovery characteristics are discussed in temperature range from 300 to 500 K. The results prove that the superior electronics performance of the β -Ga ₂ O ₃ SBDs with good electronics thermal tolerance can overcome the low thermal conductivity of β -Ga ₂ O ₃ to a certain extent. The fabricated β -Ga ₂ O ₃ SBDs have great potential for high power and high-frequency applications.

A novel superjunction (SJ) LDMOS (>950 V) with a thin layer SOI (T-SJ LDMOS) combining the advantage of low specific on-resistance Ron,sp of the SJ and the high breakdown voltage VB of the thin SOI is proposed and experimentally demonstrated in this letter. Based on our previously developed equivalent substrate (ES) model, the optimized SJ endows the device with a respectably reduced Ron,sp without sacrificing VB. Meanwhile, the thin layer SOI is designed with the enhanced dielectric layer field (ENDIF) principle to carry out a high VB. The experimental results exhibit a Ron,sp of 145 mΩ·cm² with a VB of 977 V. This represents a reduction in Ron,sp by 18.1% when compared with the theoretical Ron,spα 2.5 “silicon limit”.

In this study, we proposed and experimentally demonstrated a high breakdown voltage (BV) and low dynamic ON-resistance (RON, D) AlGaN/GaN high electron mobility transistor (HEMT) by implanting fluorine ions in the thick SiNx passivation layer between the gate and drain electrodes. Instead of the fluorine ion implantation in the thin AlGaN barrier layer, the peak position and vacancy distributions are far from the two-dimensional electron gas (2DEG) channel in the case of fluorine ion implantation in the thick passivation layer, which effectively suppresses the direct current (DC) static and pulsed dynamic characteristic degradation. The fluorine ions in the passivation layer also extend the depletion region and increase the average electric field (E-field) strength between the gate and drain, leading to an enhanced BV. The BV of the proposed HEMT increases to 803 V from 680 V of the conventional AlGaN/GaN HEMT (Conv. HEMT) with the same dimensional parameters. The measured RON, D of the proposed HEMT is only increased by 23% at a high drain quiescent bias of 100 V, while the RON, D of the HEMT with fluorine ion implantation in the thin AlGaN barrier layer is increased by 98%.

A novel ultralow specific on-resistance (R _ON,sp ) SOI lateral double-diffused MOS (LDMOS) with three separated gates (TSGs) and high-k (HK) pillars is proposed and investigated by simulation. The TSGs include the planar gate (G _X ), the segmented trench gate (G _Y ) between the p+ body contact regions, and the embedded trench gate (G _Z ) connected with HK pillars and p-well regions. First, in the on-state, the TSGs form three channels, including one lateral channel and two vertical channels, which can decrease R _ON,sp significantly. Second, G _Y and G _Z are extended to the buried oxide, widening the vertical conduction area and enhancing the current density in the bulk to further reduce RON,sp. Furthermore, the electron accumulation layer (EAL) is formed not only beside the extended G _Y and G _Z , but also along the sidewall of the drift region near the source side, thus reducing R _ON,sp greatly. Third, the HK pillars can increase the optimal drift doping concentration (Nd) to decrease R _ON,sp owing to the assisted depletion effect. The device obtains an ultralow R _ON,sp of 0.34 mΩ · cm ² at BV = 97 V. Compared with the conventional LDMOS and other previous devices, the TSG-HK LDMOS achieves better tradeoff between the breakdown voltage and R _ON,sp .

A novel ultra-fast snapback-free CTG RC-IGBT is proposed and investigated by simulation. It features a controllable trench gate (CTG) in the collector side and a bias voltage (V RC) is applied between the CTG and collector electrode. In the forward conduction state with V RC < 0, a high density hole inversion layer is formed around the CTG. The CTG acts as not only a folded controllable hole injector to enhances the hole injection efficiency, but also an electron barrier to increase the distributed resistance. The CTG RC-IGBT achieves a low on-state voltage drop (V on) and snapback-free with a small cell pitch. In the blocking state with V RC > 0, an electron accumulation layer is formed around the CTG. The electron layer together with the CTG acts as an equivalent N-buffer layer to stop the electric field and support high breakdown voltage. During turn-off, the CTG RC-IGBT behaves like a unipolar device without long tail current because the hole injection is deactivated by properly switching the V RC. Compared with conventional RC-IGBT, the proposed device decreases the V on and turn-off energy loss (E off) by 34% and 74% respectively under the load current of 100A/cm2 and bus voltage of 600V.

A novel high voltage ultra-thin silicon on insulator (SOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) with a sectional linearly doped drift region is proposed and experimentally realized in this letter. The new device features a sectional linear doping (SLD) in a 0.17 μm SOI layer with a source field plate covering the full drift region. Low specific on-resistance Ron,sp is obtained by increasing the local doping concentration of the high resistance region. An analytical model is developed to provide the design guidance for the thin SOI devices with the field plate. The experimental results of the SOI SLD-LDMOS demonstrate that the new device shows a high breakdown voltage VB of 960 V with a superior figure of merit (FOM = VB 2 / Ron,sp) of 5.98 MW/cm2 when comparing with other reported thin SOI devices. Good agreements are observed between the model and the experimental results.