A novel superjunction (SJ) LDMOS (>950 V) with a thin layer SOI (T-SJ LDMOS) combining the advantage of low specific on-resistance Ron,sp of the SJ and the high breakdown voltage VB of the thin SOI is proposed and experimentally demonstrated in this letter. Based on our previously developed equivalent substrate (ES) model, the optimized SJ endows the device with a respectably reduced Ron,sp without sacrificing VB. Meanwhile, the thin layer SOI is designed with the enhanced dielectric layer field (ENDIF) principle to carry out a high VB. The experimental results exhibit a Ron,sp of 145 mΩ·cm² with a VB of 977 V. This represents a reduction in Ron,sp by 18.1% when compared with the theoretical Ron,spα 2.5 “silicon limit”.

A novel high voltage ultra-thin silicon on insulator (SOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) with a sectional linearly doped drift region is proposed and experimentally realized in this letter. The new device features a sectional linear doping (SLD) in a 0.17 μm SOI layer with a source field plate covering the full drift region. Low specific on-resistance Ron,sp is obtained by increasing the local doping concentration of the high resistance region. An analytical model is developed to provide the design guidance for the thin SOI devices with the field plate. The experimental results of the SOI SLD-LDMOS demonstrate that the new device shows a high breakdown voltage VB of 960 V with a superior figure of merit (FOM = VB 2 / Ron,sp) of 5.98 MW/cm2 when comparing with other reported thin SOI devices. Good agreements are observed between the model and the experimental results.

A novel Homogenization Field Technology (HOFT) in lateral power devices is proposed and experimentally proved in this letter. By introducing the periodically discrete metal insulator semiconductor (MIS) structure, which realizes periodic equal potential and self-charge balance, the HOFT obtains almost uniform surface and bulk electric field distributions in the voltage sustaining layer. Therefore, the new device harvests both higher breakdown voltage VB and lower specific on-resistance Ron,sp than those of the conventional reduced surface field (RESURF) technology in much higher and wider doping dose range. The experiment of the HOFT device realized a VB of 672 V and a Ron,sp of 56.7 mΩ·cm2 under a high doping dose of 5.6 × 1012 cm−2, which represents a reduction of 33.8% when compared with the theoretical value of the triple RESURF technology.

Superjunction (SJ) structure is one of the most effective approaches to improving the performance limit between specific ON-resistance ( R _on,sp ) and breakdown voltage ( BV ) for the unipolar power device, particularly in high-voltage and high-current areas. In this letter, R _on,sp - BV performance limit of 4H-SiC SJ drift region is achieved featuring both the two-dimensional electric field and the anisotropy of impact ionization of 4H-SiC. The breakdown path is the curve from the bottom midpoint of N pillar to the top midpoint of P pillar via the midpoint of P-N pillar interface, instead of the midline of the pillar, due to that the impact ionization along [11 2 0] is stronger than that along [0001]. Moreover, a design guideline is provided for optimized R _on,sp ( R _on,opt ) under a given BV , including the width, depth, and concentration of SiC SJ drift region. SJ adoption enables SiC drift region to have a quasi-linear dependence of R _on,sp on BV , i.e., R _on,sp ∝ BV ^1.007 , which is well verified by TCAD simulation. With BV larger than 2000V, the SJ utilization can significantly reduce R _on,sp of SiC device. By determining the breakdown path, the theoretical performance limit shows huge potential of SJ approach for the high-voltage and high-current SiC device, and the practical design guideline can instruct to better design the SiC SJ device.

A novel self-modulated superjunction lateral double-diffused MOSFET (SM-SJ LDMOS) is proposed and experimentally realized in this letter. When a SJ is introduced into a lightly doped N-drift region, the 3-D depletion regions appear surrounding the P-pillars. This 3-D junction field effect transistor (JFET) effect decreases the current paths in both N-pillars and N-drift, causing a largely increased specific on-resistance Ron,sp especially for the SJ with a narrow cell pitch. To suppress the inherent 3-D JFET effect, the SM-SJ structure is proposed by replacing the P-pillars with a series of P-islands. These P-islands with linearly reduced lengths modulate the surface electric field to increase the breakdown voltage VB while the N-drift areas between P-islands weaken the 3-D JFET effect to reduce Ron,sp. Compared with the conventional SJ device, the measured VB of the SM-SJ LDMOS is increased by 53.1% from 260 V to 398 V with Ron,sp reduced by 22.3% from 35.4 mΩ·cm2 to 27.5 Ω·cm2.