Wen Luh Yang

Prof. Wen Luh Yang


Research Focus & Metrics

Academic Career Length

17Years (2010-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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23 August 2012 in IEEE Electron Device Letters
Verified
Journal Article
Closed access
SLSheng-Hsien Liu
Sheng-Hsien Liu
WYWen Luh Yang
Wen Luh Yang
Chi-Chang WuChi-Chang Wu
Chi-Chang Wu
TCTien-Sheng Chao
Tien-Sheng Chao
A novel technique combination of ion bombardment (IB) and NH3 plasma treatment (PT) has been presented to yield a highly effective charge storage layer for Si/SiO2/Si3N4/SiO2/Si (SONOS)-type nonvolatile memory applications. The IB technique creates additional trap sites within the charge storage layer strikingly to enhance the charge trapping/detrapping efficiency of the storage layer, and the NH3 PT passivates shallow trap sites significantly to improve reliability characteristics. The distribution of trap sites corresponding with various energy levels is clearly described by discharge-based multipulse analysis. As compared with the control sample (without IB and NH3 PT), the ion-bombarded and NH3-plasma-passivated memory device has faster program/erase speeds and larger memory window. In addition, the competent reliability properties of the ion-bombarded and NH3-plasma-passivated memory, such as good endurance, long data retention, and acceptable disturbance, were also demonstrated in this letter.

31 July 2013 in Discover Nano
Verified
Journal Article
Open access
PDF file
YCYuan-Ming Chang
Yuan-Ming Chang
WYWen Luh Yang
Wen Luh Yang
SLSheng-Hsien Liu
Sheng-Hsien Liu
YHYu-Ping Hsiao
Yu-Ping Hsiao
JWJia-Yo Wu
Jia-Yo Wu
CWChi-Chang Wu
Chi-Chang Wu
In this study, a high-performance Ti x Zr y Si z O flash memory is demonstrated using a sol–gel spin-coating method and formed under a low annealing temperature. The high-efficiency charge storage layer is formed by depositing a well-mixed solution of titanium tetrachloride, silicon tetrachloride, and zirconium tetrachloride, followed by 60 s of annealing at 600°C. The flash memory exhibits a noteworthy hot hole trapping characteristic and excellent electrical properties regarding memory window, program/erase speeds, and charge retention. At only 6-V operation, the program/erase speeds can be as fast as 120:5.2 μs with a 2-V shift, and the memory window can be up to 8 V. The retention times are extrapolated to 106 s with only 5% (at 85°C) and 10% (at 125°C) charge loss. The barrier height of the Ti x Zr y Si z O film is demonstrated to be 1.15 eV for hole trapping, through the extraction of the Poole-Frenkel current. The excellent performance of the memory is attributed to high trapping sites of the low-temperature-annealed, high-κ sol–gel film.

1 January 2015 in Solid-State Electronics
Verified
Journal Article
Closed access
FCFun-Tat Chin
Fun-Tat Chin
YLYu-Hsien Lin
Yu-Hsien Lin
WYWen Luh Yang
Wen Luh Yang
CLChin-Hsuan Liao
Chin-Hsuan Liao
LLLi-Min Lin
Li-Min Lin
TCTien-Sheng Chao
Tien-Sheng Chao

18 May 2010 in IEEE Electron Device Letters
Verified
Journal Article
Closed access
Chi-Chang WuChi-Chang Wu
Chi-Chang Wu
Fu-Hsiang KoFu-Hsiang Ko
Fu-Hsiang Ko
WYWen Luh Yang
Wen Luh Yang
HYHsin-Chiang You
Hsin-Chiang You
FLFu-Ken Liu
Fu-Ken Liu
CCChing-Hwa Cheng
Ching-Hwa Cheng
A new sol-gel-derived TixZrySizO nanocrystal (NC) memory with a high-performance data retention characteristic is demonstrated by the hot-hole-trapping method. Prior to rapid thermal annealing, the high-density NC layer is formed by depositing a well-mixed solution of titanium tetrachloride, silicon tetrachloride, and zirconium tetrachloride. The electrical properties of the sol-gel-derived NC memory are demonstrated in terms of memory window, charge retention, program speed, and endurance. The memory window of the NC memory from the novel hot-hole-trapping mechanism can be achieved up to 4.18 ± 0.21 V, and long retention times obtained from extrapolation up to 106 s are observed as 8%, 13%, and 21% window narrowing under respective temperatures of 25 °C, 85 °C, and 125 °C. The good electrical performance is attributed to the contribution of the high density of isolated NCs and hole-trapped into the deep-trap energy level, so no significant lateral and vertical charge leakage occurs.

22 December 2016 in Physica Status Solidi (a)
Verified
Journal Article
Closed access
PDF file
LLLi‐Min Lin
Li‐Min Lin
WYWen Luh Yang
Wen Luh Yang
YLYu‐Hsien Lin
Yu‐Hsien Lin
YHYu‐Ping Hsiao
Yu‐Ping Hsiao
FCFun‐Tat Chin
Fun‐Tat Chin
MKMing‐Fang Kao
Ming‐Fang Kao

28 October 2014 in Discover Nano
Verified
Journal Article
Open access
PDF file
FCFun-Tat Chin
Fun-Tat Chin
YLYu-Hsien Lin
Yu-Hsien Lin
HYHsin-Chiang You
Hsin-Chiang You
WYWen Luh Yang
Wen Luh Yang
LLLi-Min Lin
Li-Min Lin
TCTien-Sheng Chao
Tien-Sheng Chao
This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO2-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO2 interface and the thickness of the SiO2 layer obtained by CDT-based Cu deposition on SiO2 were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO2-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO2-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.