We fabricated the HfZrO ₂ (HZO) ferroelectric fin field-effect transistors (Fe-FinFET) with fin width of 60 nm and gate length of 100 nm for ferroelectric nonvolatile memory operations. The fabricated Fe-FinFET exhibited a large memory window (MW) of 1.5 V and high (100 ns) program/erase speeds at ±5 V. After 10 ⁵ program/erase cycles, the MW was maintained at 1.09 V and the retention time was measured up to 10 ⁴ s with no degradation. The fabricated HZO Fe-FinFET is compatible with the current FinFET process and has a high MW, a fast program/erase speed, and excellent reliability. Therefore, the fabricated Fe-FinFET is a promising candidate for high-density ferroelectric field-effect transistor memory applications.

Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure. These structures offer more $\text{W}_{\mathrm{ eff}}$ per existing footprint and better parallel resistance, resulting in smaller total resistance. Also, the GAA stacked NS device shows superior electrical properties, including high Ion/Ioff ratio ( $> 10^{8}$ ), steep subthreshold swing (SS) = 100 mV/dec, very low drain-induced-barrier-lowering (DIBL) = 0.127 mV/V and usually off at Vg = 0 V, owing to superior gate controllability. More, the 3D TCAD simulation has applied for analysis of physical characteristics of the proposed devices.

This study comprehensively investigated a junctionless thin-film transistor (JL TFT) with stacked nanosheet (NS) channels. Through experiments, we 1) compared a JL TFT with a single NS channel and a JL TFT with stacked NS channels and 2) compared an inversion-mode TFT with stacked NS channels and the JL TFT with stacked NS channels; the TFTs were fabricated using Si-based technology. The JL TFT with stacked NS channels exhibited a subthreshold slope of 135 mV/dec and drain-induced barrier-lowering value of $50.8 \text{mVV}^1$ , which were superior to those of the other devices. Furthermore, we simulated another device with a hybrid P/N/P channel structure based on the JL TFT by using three-dimensional technology computer aided design (3D TCAD) simulation. According to the study results, the JL TFT with stacked NS channels is a promising candidate for scaling down Si TFTs and for use in advanced 3D applications.

This study investigated the temperature effect on amorphous indium gallium zinc oxide (a‐IGZO) thin film transistors (TFTs) using hafnium oxide (HfO₂) gate dielectric material. HfO₂ is an attractive candidate as a high‐κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chemical reaction of the IGZO thin film and enhancing the gate oxide quality to adjust the electrical characteristics of the TFTs. However, the hafnium atom diffused the IGZO thin film, causing interface roughness because of the stability of the HfO₂ dielectric thin film during high‐temperature annealing. In this study, the annealing temperature was optimized at 200°C for a HfO₂ gate dielectric TFT exhibiting high mobility, a high I_ON/I_OFF ratio, low I_OFF current, and excellent subthreshold swing (SS).

This work demonstrates the gate-all-around P/N hybrid nanosheet (NS) p-channel junctionless field-effect transistors (GAA NS-JLFET) with trench and raised source and drain structure. The GAA NS-JLFET exhibits the superior electrical properties, including high field-effect mobility (18.9 cm2/Vs), high ON/OFF current ratio (>5$\times10^6$), steep subthreshold slope (136 mV/dec.), and low DILB (60 mV/V). The high mobility and steep subthreshold slope (SS) of this GAA NS-JLFET indicates that the conducting hole filled the whole thin nanosheet channel. This GAA NS-JLFET is simple to fabricate and highly favorable for use in advanced system-on-panel (SoP) and three-dimensional (3-D) stacked ICs applications.

As technology develops, the stacked nanosheet (NS) structure demonstrates promise for use in future technology nodes. This study demonstrated the excellent performance of stacked-NS channels with junctionless gate-all-around thin-film transistors and compared the electrical characteristics of single-NS and stacked-NS structures. The performance of the multi-gate and gate-all-around transistors was then further analyzed. The stacked gate-all-around thin-film transistor exhibited superior performance and excellent temperature design flexibility. In brief, the stacked gate-all-around structure for thin-film transistors structure has the potential to overcome the challenges associated with downscaling.