In-Memory Computing (IMC), which takes advantage of analog multiplication-accumulation (MAC) insides memory, is promising to alleviate the Von-Neumann bottleneck and improve the energy efficiency of deep neural networks (DNNs). Since the time-domain (TD) computing is also an energy-efficient analog computing paradigm, we present an 8kb mixed-signal IMC macro, TD-SRAM, by combining IMC with TD computing. A dual-edge single input (DESI) TD computing topology is proposed, which can significantly improve the area and power efficiencies of TD cell. The TD-SRAM bitcell consisting of a 6T DESI based TD cell and a 6T-SRAM cell supports binary DNNs. In the IMC mode, 60 columns work in parallel and 96-input binary-MAC operations are processed in each column. Implemented in a standard 40-nm CMOS process, the TD-SRAM achieves the high energy efficiency of 537 TOPS/W at 0.9-V supply. With different DNN topologies, the test chips achieve the accuracy of 95.90%–98.00% with a dual 2-bit time-to-digital converter (TDC) in the MNIST dataset.

Generally, computer-science-oriented artificial neural networks (ANNs) and neuroscience-oriented spiking neural networks (SNNs) are two main approaches to develop brain-spired non von Neumann computing systems. The goal of exploring complex artificial intelligence (AI) systems demands general neuromorphic hardware platforms compatible with both of them. However, as a result of the obvious differences in their fundamental mathematical expression and coding scheme, many neuromorphic platforms or deep neural network (DNN) accelerators accommodate only one of them. This brief presents a reconfigurable scalable neuromorphic chip based on digital leaky integrate-and-fire (LIF) neuron model targeting low-cost large-scale systems. By unifying ANN and SNN paradigms within a LIF neuron framework with point-to-point (P2P) communication, the chip can accommodate most popular neural networks. The chip adopts distributed on-chip memory architecture with a capacity of 64K neurons and 64M synapses. It achieves a peak throughput of 12.29 GSOP/s at 1.2 V, 192MHz and peak energy efficiency of 2.64 pJ/SOP at 890 mV, 24MHz. The results of implementations of a spike-based spatio-temporal memory model and ternary-weight event-based convolutional neural networks (CNNs) demonstrate outstanding compatibility of the chip.

The neuromorphic approach of fulfilling brain-like edge intelligence is confronted with three paramount challenges: 1) ever-increasing application demands versus insufficient on-chip resources; 2) diverse data sources and models versus heterogeneous computing paradigms; and 3) adaptation to real scenarios versus absence of on-chip learning. To bridge those gaps in the current research community, this article presents PAICORE, a 537.98-mm $^{2}$ digital neuromorphic processor with a unified computing and learning paradigm. PAICORE is a scalable 1024-core design, integrating over 1.919 million neurons and 4.773 billion synapses on a single chip. PAICORE is implemented in globally asynchronous locally synchronous (GALS) style with a five-level fat up–down quadtree as dedicated network-on-chip (NoC) infrastructure and tiled 2-D chip array as inter-chip architecture. The distributed processing cores fuse the hybrid spiking neural network (SNN), artificial neural network (ANN), and on-chip spike-timing-dependent plasticity (STDP) learning models into a unified description by modular-level reconfiguration. PAICORE achieves the peak performance of 20.74 TSOPS, 41.49 TOPS, and 115.25 GSOPS, with the best energy efficiency of 5.181 TSOPS/W, 10.372 TOPS/W, and 1.222 TSOPS/W for SNN, ANN, and on-chip learning paradigms, respectively. Benefiting from the PAIFLOW software framework, PAICORE hardware platform can be equivalently simulated and efficiently programmed in a large-scale deployment, in accordance with specific optimizing demands for its target multi-paradigm tasks.

Analog computing-in-memory (CIM) has been widely explored for computing neural networks (NNs) efficiently. However, most analog CIM implementations trade compute accuracy for energy efficiency. The low accuracy restricts the practical application of analog CIM. In this article, a current-programming CIM that unifies the weight programming and computing in the current domain is proposed to address this dilemma. The enabled technique is a novel 3-transistor 1-capacitor (3T1C) embedded dynamic random access memory (eDRAM) cell. The current-programming mechanism and the dynamic-cascode read structure of the 3T1C cell make it immune to transistor-level non-idealities, including nonlinear $I$ – $V$ , threshold voltage variations, and short-channel effect. Therefore, the cell enables multi-level-cell (MLC) operations without any calibration, supporting eight current-weight levels (0–700 nA). In addition, a voltage–current two-step programming scheme is proposed to boost the sub-microamphere current-weight writing speed. To support signed 4-b weights, a pseudo-differential CIM cell composed of two 3T1C MLCs is developed. Fabricated in a 65-nm CMOS, the prototype demonstrates 2.2 $\times $ reduction in macro-level variation through current programming. Benefiting from sub-microamphere compute currents, the prototype achieves the 4-b energy efficiencies of 233–304 TOPS/W. With a refresh interval of 0.4 ms, the macro achieves >90% inference accuracy on CIFAR10.

This article presents a compact, robust, and transposable SRAM in-memory computing (IMC) macro to support feed forward (FF) and back propagation (BP) computation within a single macro. The transpose macro is created with a clustering structure, and eight 6T bitcells are shared with one charge-domain computing unit (CCU) to efficiently deploy the DNNs weights. The normalized area overhead of clustering structure compared to 6T SRAM cell is only 0.37. During computation, the CCU performs robust charge-domain operations on the parasitic capacitances of the local bitlines in the IMC cluster. In the FF mode, the proposed design supports 128-input 1b XNOR and 1b AND multiplications and accumulations (MACs). The 1b AND can be extended to multi-bit MAC via bit-serial (BS) mapping, which can support DNNs with various precision. A power-gated auto-zero Flash analog-to-digital converter (ADC) reducing the input offset voltage maintains the overall energy efficiency and throughput. The proposed macro is prototyped in a 28-nm CMOS process. It demonstrates a 1b energy efficiency of $166\vert 257$ TOPS/W in FF-XNOR $\vert $ AND mode, and 31.8 TOPS/W in BP mode, respectively. The macro achieves $80.26\% \vert 85.07\%$ classification accuracy for the CIFAR-10 dataset with 1b $\vert 4\text{b}$ CNN models. Besides, 95.50% MNIST dataset classification accuracy (95.66% software accuracy) is achieved by the BP mode of the proposed transpose IMC macro.