This article presents an energy-efficient comparator design. The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting $g_{m}/I_{D}$ and reducing noise. Moreover, it greatly reduces the influence of the process corner and the input common-mode voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180 nm achieves 46- $\mu \text{V}$ input-referred noise while consuming only 1 pJ per comparison under a 1.2-V supply. This represents greater than seven-time energy efficiency boost compared with a strong-arm (SA) latch. It achieves the highest reported comparator energy efficiency to the best of our knowledge.

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.

This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed closed-loop dynamic amplifier combines the merits of closed-loop architecture and dynamic operation, realizing robustness, high accuracy, and high energy-efficiency simultaneously. It is embedded in the loop filter of an NS SAR design, enabling the first fully dynamic NS-SAR ADC that realizes sharp noise transfer function (NTF) while not requiring any gain calibration. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 83.8 dB over a bandwidth of 625 kHz while consuming only 107 μW. It results in an SNDR-based Schreier figure-of-merit (FoM) of 181.5 dB.

The Noise-Shaping (NS) SAR is an attractive new ADC architecture that emerged in the last decade. It combines the advantages of the SAR and the DSM architectures. NS SAR shows excellent potential for high efficiency and low cost, and is highly suited to process scaling. This paper gives an overview of the history of NS-SAR, reviews the fundamentals challenges, and summarizes the latest developments, including advanced loop filtering techniques, DAC mismatch mitigation, kT/C mitigation, and bandwidth boosting. A comprehensive comparison of the state-of-the-art NS-SAR ADCs is provided, and conclusions are derived.

As any analog-to-digital converter (ADC) with a front-end sample-and-hold (S/H) circuit, successive approximation register (SAR) ADC suffers from a fundamental signal-to-noise ratio (SNR) challenge: its sampling kT/C noise. To satisfy the SNR requirement, the input capacitor size has to be sufficiently large, leading to a great burden for the design of the ADC input driver and reference buffer. This article presents an SAR ADC with a kT/C noise-cancellation technique. It enables the substantial reduction of ADC input capacitor size but without the large kT/C noise penalty. It greatly relaxes the requirement for ADC input driver and reference buffer. Built in 40-nm CMOS, a prototype 13-bit ADC has only 240-fF input capacitance and occupies a small area of 0.005 mm². Operating at 40 MS/s, it achieves a 69-dB signal-to-noise-and-distortion ratio (SNDR) across the Nyquist frequency band while consuming 591 μW of power.

Compared with the tremendous advancements of digital IC design automation over the last few decades, analog IC layout is still heavily manual, which is very tedious and error-prone. This is partially due to the sensitive layout dependent effects, but most important of all, the lack of readily available tools to designers. In this work, we present MAGICAL, an open-sourced, fully-automated analog IC layout system. MAGICAL is capable of handling system-level designs and generates GDSII format layout from unannotated netlists. We also introduce the various extensions that build on top of the original MAGICAL framework, successfully incorporating machine learning techniques for efficient, performance-driven analog layout synthesis. We hope that our works could contribute to the open-source EDA community and promote research in developing novel algorithms and methods for analog design automation.