The number of IoT devices has grown significantly in recent years, and edge computing in IoT is considered a new and growing trend in the technology industry. While cryptography is widely used to enhance the security of IoT devices, it also carries limitations such as resource constraints or latency. Therefore, lightweight cryptography (LWC) balances commensurate resource usage and maintaining security while minimizing system costs. The ASCON stands out among the LWC algorithms as a potential target for implementation and cryptoanalysis. It provides authenticated encryption with associated data (AEAD) and hashing functionalities in many variants, aiming for various applications. In this brief, we present an implementation of Ascon cryptography as a peripheral of a RISC-V System-on-a-Chip (SoC). The ASCON crypto core occupies 1,424 LUTs in FPGA and 17.4 kGE in 180nm CMOS technology while achieving 417 Gbits/J energy efficiency at a supply voltage of 1.0V and frequency of 2 MHz.

A Trusted Execution Environment (TEE) sets a platform to secure applications based on the Chain-of-Trust (CoT). The starting point of the CoT is called the Root-of-Trust (RoT). However, the RoT implementation often relies on obscurity and provides little flexibility when generating keys to the system. In this paper, a TEE System-on-a-Chip (SoC) architecture is proposed based on a heterogeneous design by combining 64-bit Linux-capable processors with a 32-bit Micro-Controller Unit (MCU). The TEE is built on the 64-bit cores, while the 32-bit MCU takes care of sensitive data and activities. The MCU is isolated from the TEE side by an Isolated Bus (IBus) that sits above the conventional System Bus (SBus). Besides the 32-bit processor, the isolated sub-system contains a Random Access Memory (RAM), a Read-Only Memory (ROM) for storing the boot program, and another ROM for storing root keys. For cryptography accelerators, we have 512-bit Secure Hashing Algorithm 3 (SHA3-512), 128/256-bit Advanced Encryption Standard (AES-128/256), Ed25519, and True Random Number Generator (TRNG) attached to the Peripheral Bus (PBus). Additionally, besides the public channel, the TRNG module also has a private channel that goes directly to the IBus. With RoT implemented inside the isolated sub-system, the RoT is inaccessible from the TEE side after boot. Furthermore, the hidden MCU’s secure boot program makes the key generation flexible and could be updated for many security schemes. To summarize, the proposed design features a flexible and secure boot procedure with complete isolation from the TEE domain. Moreover, exclusive secure storage for the root key and cryptographic accelerators are available for the boot process. The implementation was tested on a Virtex-7 XC7VX485T Field-Programmable-Gate-Array (FPGA). It was also synthesized in a Very Large-Scale Integrated (VLSI) circuit with the ROHM-180nm process library.

All cryptography systems have a True Random Number Generator (TRNG). In the process of validating, these systems are necessary for prototyping in Field Programmable Gate Array (FPGA). However, TRNG uses an entropy source based on non-deterministic effects challenging to replicate in FPGA. This work shows the problems and solutions to implement an entropy source based on frequency collapse in multimodal Ring Oscillators (RO). The entropy source implemented in FPGA pass all SP800-90B tests from the National Institute of Standards and Technology (NIST) with a good entropy compared to related works. The TRNG passes all NIST SP800-22 with and without the post-processing stage. Besides, the TRNG and the post-processing stage pass all tests of Application notes and Interpretation of the Scheme (AIS31). The TRNG implementation on a Xilinx Artix-7 XC7A100TCSG324 FPGA occupies less than 1% of the resources. This work presents 0.62 μs up to 9.92 μs of sampling latency and 1.1 Mbps up to 9.1 Mbps of bit rate throughput.

To facilitate the integration of the NIST-standardized post-quantum cryptographic (PQC) algorithm, Module Lattice-based Key Encapsulation Mechanism (ML-KEM), into quantum-resistant devices and cryptosystems, this study introduces an area-time efficient hardware implementation. We propose several key optimizations: a dedicated SHA3 design merging hashing and sampling to eliminate hash output storage, a high-performance polynomial arithmetic unit with a novel reuse technique that reduces twiddle factor storage by threefold, and a partitioned storage strategy to minimize memory footprint. By tightly coupling pipelining and parallelism, we further enhance execution speed and avoid memory access bottlenecks. Our FPGA-based ML-KEM implementation achieves a superior area-time product (ATP), outperforming state-of-the-art results by up to 6.7× across NIST security levels 1, 3, and 5. A 180 nm CMOS fabrication of our design yields a die area of 1,940×1,789 μm². Measured performance shows the lowest SRAM requirement (7.37 kB) and minimal energy consumption (6.4 μJ, 10.3 μJ, and 14.4 μJ for security levels 1, 3, and 5), leading to ATP improvements ranging from 1.5× to 115.0× compared to existing ASIC solutions.

The Internet-of-Things applications use embedded processors to execute lightweight tasks for sensing and management of communications. These applications use different energy reducing strategies such as clock gating and domain switching. However, some power supplies for sensor systems are designed for low-power delivery rather than low-energy battery consumption. Regarding power consumption, it is important to choose the system-based processor in which some variables are taken into account. Depending on the final IoT application, such variables are power consumption, area, performance, and software tools. This brief presents an 8bits and 32bits based System on Chip (SoC) in a General Purpose (GP) CMOS technology. The two processors are implemented in the same tape-out and the same peripherals. The experiment results show a $1.69~\mu \text{W}$ and $1.76~\mu \text{W}$ in the 32bits and 8bits SoC, respectively. In terms of area, the 32bits processor is 46% overhead of the 8bits processor, with 6.6-kGE over 3.6-kGE. Finally, the 32bits SoC presents a 1.11 DMIPS and 8bits SoC a 1.38 DMIPS.

The Trusted Execution Environment (TEE) is designed to establish a safe environment that prevents the execution of unauthenticated programs. The nature of TEE is a continuous verification process with hashing, signing, and verifying. Such a process is called the Chain-of-Trust, derived from the Root-of-Trust (RoT). Typically, the RoT is pre-programmed, hard-coded, or embedded in hardware, which is locally produced and checked before booting. The TEE employs various cryptographic processes throughout the boot process to verify the authenticity of the bootloader. It also validates other sensitive data and applications, such as software connected to the operating system. TEE is a self-contained environment and should not serve as the RoT or handle secure boot operations. Therefore, the issue of implementing hardware for RoT has become a challenge that requires further investigation and advancement. The main objective of this proposal is to introduce a secured RISC-V-based System-on-Chip (SoC) architecture capable of securely booting a TEE using a versatile boot program while maintaining complete isolation from the TEE processors. The suggested design has many cryptographic accelerators essential for the secure boot procedure. Furthermore, a separate 32-bit MicroController Unit (MCU) is concealed from the TEE side. This MCU manages sensitive information, such as the root key, and critical operations like the Zero Stage BootLoader (ZSBL) and key generation program. Once the RoT is integrated into the isolated sub-system, it becomes completely unavailable from the TEE side, even after booting, using any method. Besides providing a secured boot flow, the system is integrated with essential crypto-cores supporting Transport Layer Security (TLS) 1.3. The chip is finally fabricated using the Complementary Metal–Oxide–Semiconductor (CMOS) 180 nm process.