The efficiency of polynomial multiplication execution majorly impacts the performance of lattice-based post-quantum cryptosystems. In this research, we propose a high-speed hardware architecture to accelerate polynomial multiplication based on the Number Theoretic Transform (NTT) in CRYSTAL-Kyber and CRYSTAL-Dilithium. We design a Digital Signal Processing (DSP) architecture for modular multiplication in butterfly and Point-Wise Multiplication (PWM) operations. Our method reduces the critical path delay of an n-bit multiplier to that of a (2n-2)-bit adder, optimizing both area and speed. These dedicated DSPs are employed in butterfly and PWM operations, completely eliminating the pre-process and post-process of NTT transforms. Furthermore, we introduce a novel unified pipelined architecture for the NTT and Inverse NTT (INTT) transformations of Kyber and Dilithium, with corresponding high-speed (Radix-2) and ultra high-speed (Radix-4) versions. Lastly, we construct a complete hardware accelerator for polynomial matrix-vector multiplication in Kyber. The Field-Programmable Gate Array (FPGA) implementation results have proven that our designs have significantly improved execution time by 3.4×–9.6× for the NTT transforms in Dilithium and 1.36×–34.16× for Kyber polynomial multiplication, compared to previous studies reported to date. Additionally, the hardware footprint results indicate that our proposed architectures exhibit superior hardware performance in Area-Time-Product (ATP), corresponding to a 44%–96% improvement. The proposed architectures are efficient and well-suited for high-performance lattice-based cryptography systems.

Quantum computing raises questions about the security of data encrypted using modern methods. Hence, the National Institute of Standards and Technology (NIST) has undertaken standardization of post-quantum cryptography (PQC) algorithms to defend against attacks from both classical and quantum computers. Following four rounds of evaluation, CRYSTALS-Kyber has been selected for standardization. In this paper, we present an efficient hardware architecture of CRYSTALS-Kyber for resource-constrained IoT devices. Firstly, we propose a compact hash module for CRYSTALS-Kyber. A single buffer is designed to perform padding, hashing, and holding data. Hence, using large FIFOs for data input/output is eliminated. Then, we propose a novel non-memory-based iterative number theoretic transform (NMI-NTT) architecture. Finally, the data flow between modules is optimized to improve parallelization and execution time. Implementation results on an Artix-7 FPGA show that our design consumes minimal hardware resources compared to the designs reported to date, corresponding to 5487 LUTs, 3426 FFs, 1548 SLICEs, 3.5 BRAMs, and 2 DSPs. Our design computes key generation, encapsulation, and decapsulation phases in 3.3/4.5/6.1 K-cycles for Kyber512, 5.6/7.1/9.2 K-cycles for Kyber768, and 8.5/10.1/12.9 K-cycles for Kyber1024, with 185MHz operating frequency. Our area-time-product (ATP) performance outperforms other designs.

The number of IoT devices has grown significantly in recent years, and edge computing in IoT is considered a new and growing trend in the technology industry. While cryptography is widely used to enhance the security of IoT devices, it also carries limitations such as resource constraints or latency. Therefore, lightweight cryptography (LWC) balances commensurate resource usage and maintaining security while minimizing system costs. The ASCON stands out among the LWC algorithms as a potential target for implementation and cryptoanalysis. It provides authenticated encryption with associated data (AEAD) and hashing functionalities in many variants, aiming for various applications. In this brief, we present an implementation of Ascon cryptography as a peripheral of a RISC-V System-on-a-Chip (SoC). The ASCON crypto core occupies 1,424 LUTs in FPGA and 17.4 kGE in 180nm CMOS technology while achieving 417 Gbits/J energy efficiency at a supply voltage of 1.0V and frequency of 2 MHz.

In cryptography, elliptic curve cryptography (ECC) is considered an efficient and secure method to implement digital signature algorithms (DSAs). ECC plays an essential role in many security applications, such as transport layer security (TLS), internet protocol security (IPsec), and wireless sensor networks (WSNs). The proposed designs of ECC hardware implementation only focus on a single ECC variant and use many resources. These proposals cannot be used for resource-constrained applications or for the devices that need to provide multiple levels of security. This work provides a multi-functional elliptic curve digital signature algorithm (ECDSA) and Edwards-curve digital signature algorithm (EdDSA) hardware implementation. The core can run multiple ECDSA/EdDSA algorithms in a single design. The design consumes fewer resources than the other single-functional design, and is not based on digital signal processors (DSP). The experiments show that the proposed core could run up to 112.2 megahertz with Virtex-7 devices while consuming only 10,259 slices in total.

Substitution boxes (S-Boxes) are essential elements of modern block ciphers, serving as non-linear characteristics that enhance the resistance of these ciphers against cryptanalysis. This research presents a new approach for constructing lightweight S-Boxes that possess strong cryptographic characteristics by combining an enhanced logistic map and an enhanced sine map. The proposed novel algorithm has optimized multiple parameters according to the security threshold set. This study has conducted the most comprehensive evaluation of criteria for S-Boxes to date. The analysis results of the generated $4\times 4$ and $5\times 5$ S-Boxes have achieved optimal criteria in terms of the Strict Avalanche Criterion (SAC) and the Bit Independence Criterion (BIC) that no previous S-Boxes have achieved. Furthermore, parameters related to side-channel attack resistance have been optimized in the design stage of S-Boxes. The constructed S-Boxes with high security can be applied to replace S-Boxes of the same size in existing algorithms or to develop lightweight block cipher algorithms. This research has made a significant contribution to the construction of S-Boxes.

With the rising data evolution, the demand for secured communications over networks is rising immensely. Elliptic Curve Cryptography (ECC) provides an attractive solution to fulfill the requirements of modern network applications. Many proposals published over the year over different variants of ECC satisfied some of the issues. Nevertheless, modern network applications such as Internet-of-Thing (IoT) and Software-Defined Networking (SDN) put the requirements on various aspects and can only be solved by different ECC algorithms. Looking at this point of view, an efficient architecture that could combine multiple ECC algorithms becomes an urgent request. In addition, even though many investigations of ECC on Field-Programmable Gate Arrays (FPGA), an efficient architecture that could be well-deployed on Application-Specific Integrated Circuit (ASIC) needs to get more study. Therefore, this paper proposes an area-efficient ECC hardware design that could integrate multiple ECC algorithms. The proposed design is deployed on both ASIC and FPGA platforms. Four well-known ECC-based Digital Signature Algorithms (DSAs), which are the Edwards-curve Digital Signature Algorithm (EdDSA) with Curve25519, Elliptic Curve Digital Signature Algorithm (ECDSA) with National Institute of Standards and Technology (NIST) Curve P-256, P-384, and P-521, are implemented. Furthermore, the design supports all DSA schemes: public-key generation, signature generation, and verification. We also provide optimized calculation flows for modular multiplication, modular inversion, point addition, point doubling, and Elliptic Curve Point Multiplication (ECPM) for two different elliptic curves: the NIST curve and Edward curve, on a unique architecture. The calculation processes are designed in projective coordinates and optimized in time and space to achieve a high level of parallelism. The proposed ECC processor could run up to 102-MHz on ASIC 180-nm and 109.7-MHz on Xilinx Virtex-7. In terms of area, The processor occupies 377,471 gates with 4.87- mm ² on the ASIC platform and 11,401 slices on the FPGA platform. The experimental results show that our combinational design achieves area-efficient even when compared with other single-functional architecture on both ASIC and FPGA.