Quantum computing raises questions about the security of data encrypted using modern methods. Hence, the National Institute of Standards and Technology (NIST) has undertaken standardization of post-quantum cryptography (PQC) algorithms to defend against attacks from both classical and quantum computers. Following four rounds of evaluation, CRYSTALS-Kyber has been selected for standardization. In this paper, we present an efficient hardware architecture of CRYSTALS-Kyber for resource-constrained IoT devices. Firstly, we propose a compact hash module for CRYSTALS-Kyber. A single buffer is designed to perform padding, hashing, and holding data. Hence, using large FIFOs for data input/output is eliminated. Then, we propose a novel non-memory-based iterative number theoretic transform (NMI-NTT) architecture. Finally, the data flow between modules is optimized to improve parallelization and execution time. Implementation results on an Artix-7 FPGA show that our design consumes minimal hardware resources compared to the designs reported to date, corresponding to 5487 LUTs, 3426 FFs, 1548 SLICEs, 3.5 BRAMs, and 2 DSPs. Our design computes key generation, encapsulation, and decapsulation phases in 3.3/4.5/6.1 K-cycles for Kyber512, 5.6/7.1/9.2 K-cycles for Kyber768, and 8.5/10.1/12.9 K-cycles for Kyber1024, with 185MHz operating frequency. Our area-time-product (ATP) performance outperforms other designs.

Substitution boxes (S-Boxes) are essential elements of modern block ciphers, serving as non-linear characteristics that enhance the resistance of these ciphers against cryptanalysis. This research presents a new approach for constructing lightweight S-Boxes that possess strong cryptographic characteristics by combining an enhanced logistic map and an enhanced sine map. The proposed novel algorithm has optimized multiple parameters according to the security threshold set. This study has conducted the most comprehensive evaluation of criteria for S-Boxes to date. The analysis results of the generated $4\times 4$ and $5\times 5$ S-Boxes have achieved optimal criteria in terms of the Strict Avalanche Criterion (SAC) and the Bit Independence Criterion (BIC) that no previous S-Boxes have achieved. Furthermore, parameters related to side-channel attack resistance have been optimized in the design stage of S-Boxes. The constructed S-Boxes with high security can be applied to replace S-Boxes of the same size in existing algorithms or to develop lightweight block cipher algorithms. This research has made a significant contribution to the construction of S-Boxes.

To facilitate the integration of the NIST-standardized post-quantum cryptographic (PQC) algorithm, Module Lattice-based Key Encapsulation Mechanism (ML-KEM), into quantum-resistant devices and cryptosystems, this study introduces an area-time efficient hardware implementation. We propose several key optimizations: a dedicated SHA3 design merging hashing and sampling to eliminate hash output storage, a high-performance polynomial arithmetic unit with a novel reuse technique that reduces twiddle factor storage by threefold, and a partitioned storage strategy to minimize memory footprint. By tightly coupling pipelining and parallelism, we further enhance execution speed and avoid memory access bottlenecks. Our FPGA-based ML-KEM implementation achieves a superior area-time product (ATP), outperforming state-of-the-art results by up to 6.7× across NIST security levels 1, 3, and 5. A 180 nm CMOS fabrication of our design yields a die area of 1,940×1,789 μm². Measured performance shows the lowest SRAM requirement (7.37 kB) and minimal energy consumption (6.4 μJ, 10.3 μJ, and 14.4 μJ for security levels 1, 3, and 5), leading to ATP improvements ranging from 1.5× to 115.0× compared to existing ASIC solutions.

Substitution boxes (S-Boxes) function as essential nonlinear elements in contemporary cryptographic systems, offering robust protection against cryptanalytic attacks. This study presents a novel technique for generating compact 8-bit S-Boxes based on multiplication in the Galois Field GF(24). The goal of this method is to create S-Boxes with low hardware implementation cost while ensuring cryptographic properties. Experimental results indicate that the suggested S-Boxes achieve a nonlinearity value of 112, matching the AES S-Box. They also maintain other cryptographic properties, such as the Bit Independence Criterion (BIC), the Strict Avalanche Criterion (SAC), Differential Approximation Probability, and Linear Approximation Probability, within acceptable security thresholds. Notably, compared to existing studies, the proposed S-Box architecture demonstrates enhanced hardware efficiency, significantly reducing resource utilization in implementations. Specifically, the implementation cost of the S-Box consists of 31 XOR gates, 32 two-input AND gates, 6 two-input OR gates, and 2 MUX21s. Moreover, this work provides a thorough assessment of the S-Box, covering cryptographic properties, side channel attacks, and implementation aspects. Furthermore, the study estimates the quantum resource requirements for implementing the S-Box, including an analysis of CNOT, Toffoli, and NOT gate counts.

Polynomial modular multiplication is the most complex and costly operation in homomorphic encryption (HE) and post-quantum cryptography (PQC). Using the Number Theoretic Transform (NTT) helps reduce the complexity of multiplication to quasi-linear O($N\,\textup{log}_{2}N$). Although NTT significantly impacts the performance of HE and PQC, existing NTT-based multipliers often fall short due to inefficient data movement and large memory overhead. Notably, deploying low-latency cryptosystems incurs more significant costs with reduced acceleration gains. To overcome these constraints, we introduce a pioneering methodology called timing-constrained NTT (TCO-NTT). We propose an innovative time-controlled memory (TCM) structure that re-orders and stores coefficients within each stage of the NTT. Then, we employ the divide-and-conquer strategy, allowing freely configurable parallelism levels. Besides, our proposed methodology can generalize to radix-2^k NTT and supports any arbitrary polynomial degree N and scale factor p values. We evaluate the proposed TCO-NTT on typical HE and PQC parameter sets across multiple levels of parallelism and radix-2^k NTT configurations. FPGA implementation results demonstrate that our TCO-NTT achieves minimal hardware cost while consistently executing the NTT in a near-theoretical execution time. Our area-time product (ATP) reports about LUT-ATP (LATP), FF-ATP (FATP), and BRAM-ATP (BATP) surpass the reported-to-date NTT designs by up to 10.2×, 17.8× and 47.2×. The proposed TCO-NTT sets new records for NTT-based multiplier efficiency, laying the foundation for implementing HE and PQC in real-time applications.

The breakdown of Moore’s Law has shifted deep learning acceleration from compute-bound to memory-bound optimization, necessitating comprehensive co-design across multiple abstraction layers. This analysis examines key co-design methodologies spanning the algorithm-architecture, architecture-physics, and integration-system domains for modern AI hardware, addressing the limitations of conventional silicon approaches. CNNs match spatial hardware arrays with tailored dataflow mapping, while GNNs manage irregular access patterns. Similarly, LLM accelerators embed key-value cache optimizations and hierarchical compression directly into the silicon, and edge inference systems adapt to physical constraints by jointly tailoring quantization at the hardware-software boundary. Furthermore, architecture and physics co-design methods, including processing-in-memory architectures, non-volatile memory interfaces, and neuromorphic computing, directly challenge von Neumann bottlenecks by integrating computation with storage at the circuit level. Chiplet ecosystems, 3D stacking, and advanced interconnect architectures enable system scaling beyond single-die limitations, with thermal management and power delivery emerging as critical factors in post-Moore hardware deployment. This survey presents a multi-level co-design perspective for AI accelerators, unifying algorithmic, architectural, and system layers through a cross-layer taxonomy and a general analytical model for computation and data movement. By synthesizing quantitative evidence across state-of-the-art designs and outlining key open challenges, it provides a structured overview of modern accelerator trends and the remaining technical gaps in the field.