Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNFETs vs. advanced technology options (ATOs) currently under consideration (e.g., silicon-germanium (SiGe) channels and progressing from today's FinFETs to gate-all-around nanowires/nanosheets). We use industry-practice physical designs of digital VLSI processor cores in future technology nodes with millions of transistors (including effects from parasitics and interconnect wires) and technology parameters extracted from experimental data. Our analysis shows that CNFETs are projected to offer 9× energy-delay product (EDP) benefit (~3× faster while simultaneously consuming ~3× less energy) compared to Si/SiGe FinFET. The ATOs provide $\lt50\%$ EDP benefits. All analyses are performed at the same off-state leakage current density ( $\le100$ nA per micron of FET width) and power density ( $\le100$ Watts per $\rm cm^2$ of chip area). This analysis provides insights into the sources of CNFET EDP benefits and addresses key questions for deeply-scaled technologies. For instance, while contact resistance is a concern for sub-10 nm nodes, CNFETs still provide up to (6.0×) EDP benefit (vs. Si/SiGe FinFETs) using CNFET contact resistance values already experimentally achieved for 9 nm contact length

Heart-rate estimation is a fundamental feature of modern wearable devices. In this paper we propose a machine learning technique to estimate heart-rate from electrocardiogram (ECG) data collected using wearable devices. The novelty of our approach lies in (1) encoding spatio-temporal properties of ECG signals directly into spike train and using this to excite recurrently connected spiking neurons in a Liquid State Machine computation model; (2) a novel learning algorithm; and (3) an intelligently designed unsupervised readout based on Fuzzy c-Means clustering of spike responses from a subset of neurons (Liquid states), selected using particle swarm optimization. Our approach differs from existing works by learning directly from ECG signals (allowing personalization), without requiring costly data annotations. Additionally, our approach can be easily implemented on state-of-the-art spiking-based neuromorphic systems, offering high accuracy, yet significantly low energy footprint, leading to an extended battery-life of wearable devices. We validated our approach with CARLsim, a GPU accelerated spiking neural network simulator modeling Izhikevich spiking neurons with Spike Timing Dependent Plasticity (STDP) and homeostatic scaling. A range of subjects is considered from in-house clinical trials and public ECG databases. Results show high accuracy and low energy footprint in heart-rate estimation across subjects with and without cardiac irregularities, signifying the strong potential of this approach to be integrated in future wearable devices.

Faster and cheaper computers have been constantly demanding technological and architectural improvements. However, current technology is suffering from three technology walls: leakage wall, reliability wall, and cost wall. Meanwhile, existing architecture performance is also saturating due to three well-known architecture walls: memory wall, power wall, and instruction-level parallelism (ILP) wall. Hence, a lot of novel technologies and architectures have been introduced and developed intensively. Our previous work has presented a comprehensive classification and broad overview of memory-centric computer architectures. In this article, we aim to discuss the most important classes of memory-centric architectures thoroughly and evaluate their advantages and disadvantages. Moreover, for each class, the article provides a comprehensive survey on memory-centric architectures available in the literature.

Neuromorphic near-sensor computing has recently emerged as a low-power and low-memory paradigm for the design of AI-enabled IoT devices working at the extreme edge. Compared to conventional sensing and learning techniques, neuromorphic sampling and processing reduces data bandwidth requirements, induces large savings on power and area consumption, and enables on-line learning and adaptation. In this article, we discuss recent studies made in the design of event-based sampling and learning circuits. We show that our event-based sampling methods outperform conventional techniques in terms of power consumption. We also show that our spiking neural network (SNN), learning through spike-timing-dependent plasticity (STDP), outperforms state-of-the-art SNN-STDP systems in terms of inference accuracy while being orders of magnitude more power efficient than conventional deep learning systems. We hope that the opportunities discussed in this summary paper will inspire future research.