In this paper, we reviewed the recent trends on neuromorphic computing using emerging memory technologies. Two representative learning algorithms used to implement a hardware-based neural network are described as a bio-inspired learning algorithm and software-based learning algorithm, in particular back-propagation. The requirements of the synaptic device to apply each algorithm were analyzed. Then, we reviewed the research trends of synaptic devices to implement an artificial neural network.

We investigate the characteristics of a synaptic imitation device using a thin-film transistor (TFT)-type NOR flash memory cell with a half-covered floating gate. The long-term potentiation (LTP) and long-term depression (LTD) required for the operation of the spike-timing-dependent plasticity (STDP) algorithm are implemented using the proposed pulse scheme. Unsupervised learning is successfully demonstrated by applying the STDP learning rule through software MATLAB simulation reflecting the LTP/LTD characteristics of the fabricated TFT-type NOR flash memory array. We present the learning and recognition processes of 28 × 28 MNIST handwritten digit patterns. First, STDP learning in a single-neuron string (784 × 1 ) is investigated, after which STDP learning is demonstrated in a multineuron array (784 × 10) with a lateral inhibition function to demonstrate the ability of multipattern learning and recognition. Meanwhile, we investigate the key factors of STDP unsupervised learning. Finally, an approach is suggested to implement a hardware neural network using the conventional CMOS technology for STDP unsupervised learning as a visual pattern recognition system.

Hardware-based spiking neural networks (SNNs) to mimic biological neurons have been reported. However, conventional neuron circuits in SNNs have a large area and high power consumption. In this work, a split-gate floating-body positive feedback (PF) device with a charge trapping capability is proposed as a new neuron device that imitates the integrate-and-fire function. Because of the PF characteristic, the subthreshold swing (SS) of the device is less than 0.04 mV/dec. The super-steep SS of the device leads to a low energy consumption of ∼0.25 pJ/spike for a neuron circuit (PF neuron) with the PF device, which is ∼100 times smaller than that of a conventional neuron circuit. The charge storage properties of the device mimic the integrate function of biological neurons without a large membrane capacitor, reducing the PF neuron area by about 17 times compared to that of a conventional neuron. We demonstrate the successful operation of a dense multiple PF neuron system with reset and lateral inhibition using a common self-controller in a neuron layer through simulation. With the multiple PF neuron system and the synapse array, on-line unsupervised pattern learning and recognition are successfully performed to demonstrate the feasibility of our PF device in a neural network.

Hardware-based Spiking Neural Networks (SNNs) are regarded as promising candidates for the cognitive computing system due to its low power consumption and highly parallel operation. In this paper, we train the SNN in which the firing time carries information using temporal backpropagation. The temporally encoded SNN with 512 hidden neurons achieved an accuracy of 96.90% for the MNIST test set. Furthermore, the effect of the device variation on the accuracy in temporally encoded SNN is investigated and compared with that of the rate-encoded network. In a hardware configuration of our SNN, NOR-type analog memory having an asymmetric floating gate is used as a synaptic device. In addition, we propose a neuron circuit including a refractory period generator for temporally encoded SNN. The performance of the 2-layer neural network composed of synapses and proposed neurons is evaluated through circuit simulation using SPICE based on the BSIM3v3 model with 0.35 μm technology. The network with 128 hidden neurons achieved an accuracy of 94.9%, a 0.1% reduction compared to that of the system simulation of the MNIST dataset. Finally, each block’s latency and power consumption constituting the temporal network is analyzed and compared with those of the rate-encoded network depending on the total time step. Assuming that the network has 256 total time steps, the temporal network consumes 15.12 times less power than the rate-encoded network and makes decisions 5.68 times faster.

A partially depleted silicon-on-insulator MOSFET is analyzed over a wide temperature range from 380K to 80K to characterize memory performance at cryogenic temperatures and verify its feasibility as a cryogenic memory cell. In the Shockley-Read-Hall theory, the generation–recombination rate decreases with decreasing temperature, therefore, the retention properties of the capacitorless single transistor DRAM cell are greatly improved as temperature decreases. The static and dynamic retention times increase sharply as temperature decreases. The dynamic retention time reaches up to ∼ 3.5 s at 80K, which is ∼104 times larger than that at 300K. In addition, as the temperature decreases, the current sensing margin also increases more than 2.5 times at 80K (∼ 11 μA) compared to that at 300K, due to the improved dynamic retention characteristics and the increased transconductance.