A partially depleted silicon-on-insulator MOSFET is analyzed over a wide temperature range from 380K to 80K to characterize memory performance at cryogenic temperatures and verify its feasibility as a cryogenic memory cell. In the Shockley-Read-Hall theory, the generation–recombination rate decreases with decreasing temperature, therefore, the retention properties of the capacitorless single transistor DRAM cell are greatly improved as temperature decreases. The static and dynamic retention times increase sharply as temperature decreases. The dynamic retention time reaches up to ∼ 3.5 s at 80K, which is ∼104 times larger than that at 300K. In addition, as the temperature decreases, the current sensing margin also increases more than 2.5 times at 80K (∼ 11 μA) compared to that at 300K, due to the improved dynamic retention characteristics and the increased transconductance.

In _0.08 Al _0.92 N/GaN fin-type high-electron mobility transistors (fin-HEMTs) with different gate-to-drain lengths (L _gd ) are fabricated and characterized by dc and low-frequency noise (LFN) measurements. The fabricated device with the largest L _gd exhibits the degradation of the maximum drain current and transconductance with a positive shift of the threshold voltage. LFN measurements of the In _0.08 Al _0.92 N/GaN fin-HEMTs reveal clear 1/f behavior of the noise spectra, and the minimum value is observed in the device at L _gd = 20 μm. The devices with smaller L _gd follow a carrier number fluctuation noise model owing to electron trapping/detrapping into the In _0.08 Al _0.92 N barrier layer from the 2-D electron gas (2DEG) channel. In contrast, the device with the largest L _gd shows correlated mobility fluctuations due to the large 2DEG mobility fluctuations in the large access area.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon (Poly-Si) metal-oxide-semiconductor field-effect transistor (MOSFET) with a storage layer separated using a separation oxide was designed and analyzed using technology computer-aided design (TCAD). The channel and storage layers were separated using a separation oxide to improve the inferior retention time of the conventional 1T-DRAM, and we adopted the underlap structure to reduce Shockley-Read-Hall recombination. In addition, poly-Si, which has several advantages, including low manufacturing cost and availability of high-density three-dimensional (3D) memory arrays, is used to easily fabricate silicon-on-insulator (SOI)-like structures. Accordingly, we extracted memory performance by analyzing the effect of grain boundary (GB). The proposed 1T-DRAM achieved a sensing margin of 14.10 μA/μm and a retention time of 251 ms at T = 358 K, even in the existence of a GB.