A large-scale monolithic silicon nanophotonic phased array on a chip creates and dynamically steers a high-resolution optical beam in free space, enabling emerging applications in sensing, imaging, and communication. The scalable architecture leverages sub-array structure, mitigating the impact of process variation on the phased array performance. In addition, sharing control electronics among multiple optical modulators in the scalable architecture reduces the number of digital-to-analog converters (DACs) required for an N² array from O(N²) to O(N), allowing a small silicon footprint. An optical phased array for 1550-nm wavelength with 1024 uniformly spaced optical grating antennas, 1192 optical variable phase shifters, and 168 optical variable attenuators is integrated into a 5.7 mm x 6.4 mm chip in a commercial 180-nm silicon-on-insulator RF CMOS technology. The control signals for the optical variable phase shifters and attenuators are provided by 136 DACs with 14-bit nonuniform resolution using 2.5-V input-output transistors. The implemented phased array can create 0.03° narrow optical beams that can be steered unambiguously within ±22.5°.

Silicon platform enables the monolithic realization of large-scale photonic integrated systems. Many emerging applications facilitated by silicon photonics such as optical biosensing, optical neurostimulation, optical phased arrays, holographic displays, 3D cameras, optical machine learning, and optical quantum information processing systems require the integration of a large number of optical phase modulators with modest modulation speed. Classical optical modulators are not suitable for such large-scale integration because of their inability to provide low optical loss, compact size, high efficiency, and wide optical bandwidth, all at the same time. We report a thermo-optic silicon modulator realized in a 0.0023-mm² silicon footprint of a commercial foundry silicon photonics process. The optical modulator consumes 2.56 mW for 180° phase modulation over 100-nm optical bandwidth while achieving 1.23-dB optical loss without air-gap trench or silicon undercut post-processing. Geometrical design optimization, at the core of this demonstration, is applicable to the realization of compact thermo-optic devices for large-scale programmable photonic integrated systems, with a potential to reduce power consumption roughly by an order of magnitude without sacrificing scalability and optical modulation bandwidth.

Concurrent multi-band delta-sigma modulation (CMB-DSM) with out-of-band noise cancellation is presented for the first time. A scaled replica modulator creates anti-phased quantization noise for multi-band noise cancellation, consequently reducing adjacent channel leakage and significantly relaxing the design of a multi-band RF filter to suppress undesirable out-of-band emission. A prototype digital transmitter is designed with 6th-order CMB-DSM using a loop filter with stability compensation. Experimental results show that the proposed noise cancellation technique achieves more than 15-dB suppression on the out-of-band quantization noise with LTE inter-band carrier aggregation (CA) on 856 MHz and 1450 MHz bands with 40-MHz aggregated channel bandwidth.

We present a high-efficiency transmitter architecture based on asymmetric multilevel outphasing (AMO), but with a new method of generating discrete amplitude levels from the constituent amplifiers. AMO and multilevel LINC (ML-LINC) transmitters improve their efficiency over LINC by switching the supplies of the power amplifiers (PAs) among a discrete set of voltages. This allows them to minimize the occurrence of large outphasing angles. However, it is also possible to generate a discrete set of amplitudes by varying the duty cycle of the waveform that drives the PAs. The chief advantage of this discrete pulse width modulation (DPWM) is hardware simplicity, as it eliminates the need for a fast, low-loss switching network and a selection of power supply voltages. We demonstrate this concept with a 48-MHz, 20-W peak output power AMO transmitter using a four-level DPWM. At peak output power, the measured power-added efficiency is 77.7%. For a 16-QAM signal with a 6.5-dB peak-to-average power ratio, the AMO prototype improves the average efficiency from 17.1% to 36.5% compared to the standard LINC system.

A low-loss bent waveguide with a Clothoid shape whose width is adjusted along the curvature is demonstrated. For a bend radius of 1.6 µm, the loss is reduced by 0.34 dB to less than 0.04 dB for a single S-shape bend when compared to a standard circular waveguide bend.

High-resolution electronic interface circuits for transducers with nonlinear capacitive impedance need an operational amplifier, which is stable for a wide range of load capacitance. Such operational amplifier in a conventional design requires a large area for compensation capacitors, increasing costs and limiting applications. In order to address this problem, we present a gain-boosted two-stage operational amplifier, whose frequency response compensation capacitor size is insensitive to the load capacitance and also orders of magnitude smaller compared to the conventional Miller-compensation capacitor that often dominates chip area. By exploiting pole-zero cancellation between a gain-boosting stage and the main amplifier stage, the compensation capacitor of the proposed operational amplifier becomes less dependent of load capacitance, so that it can also operate with a wide range of load capacitance. A prototype operational amplifier designed in 0.13- $\mathsf{\mu }$ m complementary metal–oxide–semiconductor (CMOS) with a 400-fF compensation capacitor occupies 900- $\mathsf{\mu }$ m ${}^2$ chip area and achieves 0.022–2.78-MHz unity gain bandwidth and over 65 ${}^{\circ }$ phase margin with a load capacitance of 0.1–15 nF. The prototype amplifier consumes 7.6 $\mathsf{\mu }$ W from a single 1.0-V supply. For a given compensation capacitor size and a chip area, the prototype design demonstrates the best reported performance trade-off on unity gain bandwidth, maximum stable load capacitance, and power consumption.