GaN technology is not only gaining traction in power and RF electronics but is also rapidly expanding into other application areas including digital and quantum computing electronics. This paper provides a glimpse of future GaN device technologies and advanced modeling approaches that can push the boundaries of these applications in terms of performance and reliability. While GaN power devices have recently been commercialized in the 15–900 V classes, new GaN devices are greatly desirable to explore both higher-voltage and ultra-low-voltage power applications. Moving into the RF domain, ultra-high frequency GaN devices are being used to implement digitized power amplifier circuits, and further advances using the hardware–software co-design approach can be expected. On the horizon is the GaN CMOS technology, a key missing piece to realize the full-GaN platform with integrated digital, power, and RF electronics technologies. Although currently a challenge, high-performance p-type GaN technology will be crucial to realize high-performance GaN CMOS circuits. Due to its excellent transport characteristics and ability to generate free carriers via polarization doping, GaN is expected to be an important technology for ultra-low temperature and quantum computing electronics. Finally, given the increasing cost of hardware prototyping of new devices and circuits, the use of high-fidelity device models and data-driven modeling approaches for technology-circuit co-design are projected to be the trends of the future. In this regard, physically inspired, mathematically robust, less computationally taxing, and predictive modeling approaches are indispensable. With all these and future efforts, we envision GaN to become the next Si for electronics.

The detection of rolling-element bearing fault can be accomplished by monitoring and interpreting a variety of signals, including the vibration, the acoustic noise, and the stator current. The existence of a bearing fault as well as its specific fault type can be readily determined by performing frequency spectral analysis on the monitored signals with various signal processing techniques. However, this traditional approach, despite being simple and intuitive, is not able to identify the severity of a bearing fault in a quantitatively manner. Moreover, it is often-times tedious and time-consuming to apply this approach to electric machines with different power ratings, as the bearing fault threshold values need to be manually calibrated for each motor running at every possible speed and carrying any possible load. This paper thus proposes a quantitative approach to estimate the bearing fault severity based on the air gap displacement profile, which is reconstructed from the mutual inductance variation profile estimated from a quantitative electrical model that only takes the stator current as input. In addition, the accuracy of the developed electrical model and the estimated bearing fault severity are validated by the simulation and experimental results, and the explicit air gap variation profile is reconstructed with the superposition of multiple Fourier Series terms estimated from the stator current via the proposed scheme. The proposed method offers a quantitative and universal bearing fault indicator that can be used to monitor bearing faults in induction machines with any power ratings and operating under any speed and load conditions.

Ferroelectric field-effect transistors (FeFETs) have been considered as promising electrically switchable nonvolatile data storage elements due to their fast switching speed, programmable conductance, and high dynamic range for neuromorphic applications. Meanwhile, FeFETs can be aggressively shrunk to the atomic scale for a high density device integration, ideally, without comprising the performance by introducing two-dimensional (2D) materials. So far, the demonstrated 2D material-based FeFETs mainly rely on mechanically exfoliated flakes, which are not favorable for large-scale industrial applications, and FeFETs based on organic ferroelectrics typically show a large writing voltage (e.g., >±20 V), making these types of memory devices impractical to be commercially viable. Here, we demonstrate that monolayer MoS₂ grown by chemical vapor deposition (CVD) can be used as a resistive switching channel to fabricate FeFETs, in which the MoS₂ channel is modulated by a hybrid gate stack of HfO₂/ferroelectric HfZrO_x thin films. The programming processes in the 2D MoS₂ FeFETs originate from the ferroelectric polarization switching, yielding two distinct write and erase states for data storage and cumulative channel conductance for artificial synapse applications. Our 2D FeFETs show a low-voltage-driven feature (<±3 V) and gate-tunable ferroelectric hysteresis characteristics. The thin HfO₂ layer in the hybrid gate stack likely plays crucial roles in preserving the ferroelectricity of the device and lowering the threshold of switching voltages through energy redistribution. Our findings open an avenue for the use of CVD-grown layered materials as the resistive switching mediums combined with HfO₂-based ferroelectrics for future energy-efficient “brain-on-a-chip” hardware.

In this paper, multi-channel capacitive sensor arrays based on microstrip band-stop filters are studied. The sensor arrays can be used to detect the proximity of objects at different positions and directions. Each capacitive sensing structure in the array is connected to an inductive element to form resonance at different frequencies. The resonances are designed to be isolated in the frequency spectrum, such that the change in one channel does not affect resonances at other channels. The inductive element associated with each capacitive sensor can be surface-mounted inductors, integrated microstrip inductors or metamaterial-inspired structures. We show that by using metamaterial split-ring structures coupled to a microstrip line, the quality factor of each resonance can be greatly improved compared to conventional surface-mounted or microstrip meander inductors. With such a microstrip-coupled split-ring design, more sensing elements can be integrated in the same frequency spectrum, and the sensitivity can be greatly improved.

Contiguous/noncontiguous carrier aggregation (CA) is one of the key features from 4G systems, which is expected to be evolved within 5G technologies. Thus, there is a need for the development of flexible, agile, and reconfigurable radio transceivers with a native support for the integration of multiple bands and multiple standards. All-digital radio-frequency (RF) transmitters have demonstrated promising potential to the design of next-generation RF transceivers. However, the simultaneous multiband transmission is still one of the key limitations of current approaches. To address this problem, this paper presents a fully digital and parallel architecture that enables the real-time design of agile and concurrent triple-band transmission. The proposed architecture is suitable for both contiguous and noncontiguous CA scenarios and considerably surpasses the state of the art in terms of frequency agility, maximum spacing between bands, and aggregated bandwidth. To enhance the system performance, an extension to a multilevel architecture based on the analog combination of pulsed waveforms is also demonstrated. Both architectures (two and seven levels) were implemented in a field-programmable gate array. Measurement results in terms of signal-to-noise ratio, error-vector magnitude, and adjacent-channel power ratio are presented and discussed. In Implementation-I, the two-level architecture presents a frequency agility from 0.1 to 2.5 GHz (with a frequency resolution of 4.88 MHz) with an aggregated bandwidth of 56.26 MHz. In Implementation-II, the seven-level design presents a frequency agility from 0.1 to 2 GHz (with a frequency resolution of 3.906 MHz) with an aggregated bandwidth of 112.5 MHz.

Concurrent multi-band delta-sigma modulation (CMB-DSM) with out-of-band noise cancellation is presented for the first time. A scaled replica modulator creates anti-phased quantization noise for multi-band noise cancellation, consequently reducing adjacent channel leakage and significantly relaxing the design of a multi-band RF filter to suppress undesirable out-of-band emission. A prototype digital transmitter is designed with 6th-order CMB-DSM using a loop filter with stability compensation. Experimental results show that the proposed noise cancellation technique achieves more than 15-dB suppression on the out-of-band quantization noise with LTE inter-band carrier aggregation (CA) on 856 MHz and 1450 MHz bands with 40-MHz aggregated channel bandwidth.