The remarkable achievements in the area of integrated optical memories and optical random access memories (RAMs) together with the rapid adoption of optical interconnects in the Datacom and Computercom industries introduce a new perspective for information storage directly in the optical domain, enabling fast access times, increased bandwidth and transparent cooperation with optical interconnect lines. This article reviews state-of-the-art integrated optical memory technologies and optical RAM cell demonstrations describing the physical mechanisms of several key devices along with their performance metrics in terms of their energy, speed and footprint. Novel applications are outlined, concluding with the scaling challenges to be addressed toward allowing light to serve as both a data-carrying and data-storage medium.

Following a decade of radical advances in the areas of integrated photonics and computing architectures, we discuss the use of optics in the current computing landscape attempting to redefine and refine their role based on the progress in both research fields. We present the current set of critical challenges faced by the computing industry and provide a thorough review of photonic Network-on-Chip (pNoC) architectures and experimental demonstrations, concluding to the main obstacles that still impede the materialization of these concepts. We propose the employment of optics in chip-to-chip (C2C) computing architectures rather than on-chip layouts toward reaping their benefits while avoiding technology limitations on the way to manycore set-ups. We identify multisocket boards as the most prominent application area and present recent advances in optically enabled multisocket boards, revealing successful 40 Gb/s transceiver and routing capabilities via integrated photonics. These results indicate the potential to bring energy consumption down by more than 60% compared to current QuickPath Interconnect (QPI) protocol, while turning multisocket architectures into a single-hop low-latency setup for even more than four interconnected sockets, which form currently the electronic baseline. We go one step further and demonstrate how optically-enabled eight-socket boards can be combined via a 256 × 256 Hipoλaos Optical Packet Switch into a powerful 256-node disaggregated system with less than 335 ns latency, forming a highly promising solution for the latency-critical rack-scale memory disaggregation era. Finally, we discuss the perspective for disintegrated computing via optical technologies as a mean to increase the number of synergized high-performance cores overcoming die area constraints, introducing also the concept of cache disintegration via the use of future off-die ultrafast optical cache memory chiplets.

Real‐time control of multiple cascaded devices is a key requirement for the development of complex silicon photonic circuits performing new sophisticated optical functionalities. This article describes how the dithering technique can be leveraged in combination with non‐invasive light probes to independently control the working point of many photonic components. The standard technique is extended by introducing the concept of orthogonal dithering signals to simultaneously discriminate the effect of different actuators, while the idea of frequency re‐use is discussed to limit the complexity of control systems in cascaded architectures. After a careful analysis of the problem, the article presents an automated feedback strategy to tune and lock photonic devices in the maxima/minima of their transfer functions with given response speed and sensitivity. The trade‐offs of this approach are discussed in detail to provide guidelines for the design of the feedback loop. Experimental demonstrations on a mesh of Mach‐Zehnder interferometers and on cascaded ring resonators are discussed to validate the proposed control architecture in different scenarios and applications.

The emergence of disaggregation in data center (DC) architectures as a way to increase resource utilization introduces significant challenges to the DC switching infrastructure, which has to ensure high bandwidth and low-latency communication along with high-radix connectivity. This paper examines the network requirements in disaggregated systems and reviews the credentials of state-of-the-art high-radix optical switch architectures. We also demonstrate a novel optical packet switch design, called $\text{Hipo}\mathit{\lambda }\text{aos}$, that satisfies these requirements by combining N-port broadcast-and-select and $\mathrm{N}\times \mathrm{N}$ arrayed waveguide grating router-based forwarding schemes in ${\mathrm{N}}^2$-port connectivity configurations. The $\text{Hipo}\mathit{\lambda }\text{aos}$ switch provides sub-μs latency and high throughput performance by utilizing distributed control and optical feed-forward buffering in a modified Spanke architecture. Feasibility of a 256 port $\text{Hipo}\mathit{\lambda }\text{aos}$ layout with a four-packet buffering stage is experimentally demonstrated at 10 Gb/s, revealing error-free performance with a mean power penalty value of 2.19 dB. Simulation analysis is carried out for a 256 node system and eight traffic profiles; this analysis reveals a low latency value of only 605 ns, with throughput reaching 85% even when employing only two-packet buffers. Finally, the architecture’s scalability up to $1024\times 1024$ designs is discussed, along with a power consumption analysis and a roadmap toward an integrated version of the switch.

Optical RAM appears to be the alternative approach towards overcoming the “Memory Wall” of electronics, suggesting use of light in RAM architectures to enable ps-regime memory access times. In this communication we take advantage of the wavelength properties of optical signals to present new architectural perspectives in optical RAM structures by introducing the WDM principles in the storage area. To this end, we report on a 4 × 4 WDM optical RAM bank architecture that exploits a novel SOA-based multi-wavelength Access Gate (WDM-AG) and a dual wavelength SOA-based SET-RESET All-Optical Flip Flop (AOFF) as fundamental building blocks. The WDM-AG enables simultaneous random access to a 4-bit optical word encoded in 8 different wavelengths, allowing for the four AOFFs of each RAM row to effectively share the same Access Gate. The scheme is shown to support a 10 Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15 mW/Gbit/s for the WDM-AG and 120 mW/Gbit/s for the AOFFs. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption, while enabling for re-configurability in optical cache mapping.

Today, the Datacenter (DC) ecosystems are fueling the demand for novel transmitter (TX) technologies complying to the off-board, on-board and chip-to-chip computing needs. This has set a new class of requirements for the TX infrastructure that should now offer multiple credentials, namely: i) high-speed, ii) O-band operation for avoiding dispersion compensation in long distances, iii) WDM capabilities for higher-throughput and multicasting/broadcasting support, and iv) tight co-packaging with low-power electronics. Silicon photonic (Si) TXs have been extensively studied towards high-speed and WDM TX engines targeting mainly C-band. Only a limited number of Si-Pho O-band TXs have been reported, however with $\leq$ 32 Gb/s/channel line-rate capabilities and with a WDM portfolio that has not been fully explored yet. In this article, we introduce a novel silicon photonic high-speed O-band TX hardware platform that can meet the current datacom and computercom interconnect requirements. We demonstrate a Ring Modulator (RM)-based 4-channel WDM TX at 4 $\times$ 40 Gb/s NRZ operation that supports wavelength parallelism in unicast operation but can also pave the way towards WDM Tx engines for the post-100 GbE transmitter era. Moreover, we present a broadband Si Mach-Zehnder modulator employed in a WDM modulation scheme of 2 $\times$ 25 Gb/s NRZ signals and demonstrate multicasting when combined with an 8 $\times$ 8 passive AWGR wavelength router, addressing the broadcasting needs of traffic usually encountered in cache-coherent multisocket settings. Finally, we further demonstrate the tight synergy of O-band Si-RM modulators with high-speed CMOS electronics, presenting a RM-based TX assembly prototype employing a fully-depleted silicon-on-insulator CMOS driver, delivering 50 Gb/s NRZ operation.