A digital predistorter, modeled by an augmented real-valued time-delay neural network (ARVTDNN), has been proposed and found suitable to mitigate the nonlinear distortions of the power amplifier (PA) along with modulator imperfections for a wideband direct-conversion transmitter. The input signal of the proposed ARVTDNN consists of Cartesian in-phase and quadrature phase (I/Q) components, as well as envelope-dependent terms. Theoretical analysis shows that the proposed model is able to produce a richer basis function containing both the desired odd- and even-order terms, resulting in improved modeling capability and distortion mitigation. Its actual performance has been validated through extensive simulations and experiments. The results show that the compensation and hardware impairment mitigation capabilities of the ARVTDNN are superior to the existing state-of-the-art real-valued focused time-delay neural network (RVFTDNN) by 3-4 dB for the adjacent channel power ratio and by 2-3 dB in terms of the normalized mean square error. Other important features of the proposed model are its reduced complexity, in terms of the number of parameters and floating-point operations, and its improved numerical stability compared to the RVFTDNN model.

Power amplifier (PA) models, such as the neural network (NN) models and the multilayer NN models, have problems with high complexity. In this article, we first propose a novel behavior model for wideband PAs, using a real-valued time-delay convolutional NN (RVTDCNN). The input data of the model is sorted and arranged as a graph composed of the in-phase and quadrature ( $I/Q$ ) components and envelope-dependent terms of current and past signals. Then, we created a predesigned filter using the convolutional layer to extract the basis functions required for the PA forward or reverse modeling. Finally, the generated rich basis functions are input into a simple, fully connected layer to build the model. Due to the weight sharing characteristics of the convolutional model’s structure, the strong memory effect does not lead to a significant increase in the complexity of the model. Meanwhile, the extraction effect of the predesigned filter also reduces the training complexity of the model. The experimental results show that the performance of the RVTDCNN model is almost the same as the NN models and the multilayer NN models. Meanwhile, compared with the abovementioned models, the coefficient number and computational complexity of the RVTDCNN model are significantly reduced. This advantage is noticeable when the memory effects of the PA are increased by using wider signal bandwidths.

Neural network (NN)-based models are perceived as being accurate models for power amplifier (PA) behavioral modeling and digital predistortion (DPD) applications. However, the complexity of NN’s models in terms of the number of coefficients increases with the memory depth, nonlinearity order, signal bandwidth, and the number of carriers. In this article, a novel augmented convolutional neural network (ACNN)-based DPD is proposed to linearize the concurrent multiband PAs. In the ACNN model, the convolution layer with a fully connected layer serves to model the intermodulation distortion (IMD), cross-modulation distortion (CMD), and nonlinearities of the concurrent multiband PA. The pooling layer in the ACNN reduces the model’s complexity. The measurement results show that the proposed DPD requires significantly fewer coefficients and floating-point operations (FLOPs) than the state-of-the-art DPDs. This model’s complexity reduction arises with the number of carriers in the multiband aggregated signal. The measurement results also show that the proposed DPD has a better linearization performance in terms of metrics, such as normalized mean square error (NMSE), adjacent channel power ratio (ACPR), and error vector magnitude (EVM).

In this article, a continuous-mode inverse class GF (CCGF⁻¹) power amplifier is introduced based on a new closed-form expression for the drain current. This analytical expression is utilized to exploit second source harmonic impedance manipulation in order to expand the design space of the output matching circuit resistively. This approach allows to diminish the complexity of the design of the load matching network at the fundamental and harmonic frequencies and to achieve wider bandwidth while simultaneously improving drain efficiency across the new optimum admittance points. Using the nonlinear model of a commercially available 10-W gallium nitride (GaN) device, load--pull and source-pull techniques are used to design a wideband CCGF⁻¹. The designed amplifier is fabricated using the selected transistor in low-temperature co-fired ceramic (LTCC) technology. Measurement results show that, over the frequency band between 3.05 and 3.85 GHz, a drain efficiency of more than 70%, 11-12.4-dB gain, and 39.9-41.4-dBm output power at 3-dB gain compression have been achieved. Although not designed for linearity, the fabricated amplifier shows an adjacent channel power ratio better than 26 dBc under a 20-MHz long-term evolution (LTE) signal having a 10.45-dB peak-to-average power ratio.

In this article, an artificial neural network (ANN)-based large-signal model (LSM) of AlGaN/GaN high electron mobility transistors (HEMTs) with accurate buffer-related trapping effects characterization and modeling is proposed. A hybrid small-signal parameter-extraction method for AlGaN/GaN HEMTs is used to acquire the parasitic parameters. To simplify the modeling procedure of the drain-source current Ids, an ANN-based model associated with the empirical equations taking into account the trapping effects, self-heating effects, and breakdown issue is developed. The low-frequency dispersions related to the buffer-related trapping effects have been well modeled by using a new empirical equation, which has been verified by small-signal S-parameters. Also, a new thermal factor KT and an improved Shockley diode equation are given in the proposed model as well. The developed LSM has been fully verified by a 2 × 100 μm AlGaN/GaN HEMT with the pulsed I-V, small-signal S-parameters, power sweep, and load-pull measurements.

The paper presents a design of a broadband high-efficiency class-E power amplifier (PA) for the advanced efficiency enhancement architectures applications. A sequential load pull methodology to design broadband class-E power amplifiers using a packaged gallium nitride power transistor is presented. Two different broadband matching synthesis techniques have been proposed using lumped elements have been presented and implemented in the manuscript. A fourth-order low-pass impedance transformation topology is designed as the output matching network to provide the optimum load reflection coefficients in the targeted bandwidth (1.8-2.7 GHz). A combination of input and output matching network has been proposed in the manuscript to satisfy the given fractional bandwidth requirements. For practical validation, a Wolfspeed (Cree) CGH40025 package transistor has been used. Under continuous wave test condition the fabricated PA showed more than 50% power added efficiency (PAE) with up to 29 W output power for 40% fractional bandwidth from 1.8-2.7 GHz. Furthermore, the proposed broadband Class E PA is deployed in efficiency enhancement architecture like delta-sigma modulation based transmitters. The PA shows more than 48% PAE all over the frequency band when driven with a delta-sigma modulated LTE downlink signal while maintaining high signal quality and PA reliability.