This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively.

This paper presents the principle, design, and analysis of a bi-directional gated ring oscillator (BDGRO) time integrator for time-based signal processing. The time integrator features full compatibility with technology, rapid integration, low power consumption, a virtually unlimited dynamic range, built-in dynamic element matching, and self-digitization. A detailed analysis of the impact of the imperfections of the time integrator including nonlinearity, skew, supply voltage noise, device noise, and metastability-induced gating errors is provided, supported with simulation results. The time integrator is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Virtuoso/Spectre with BSIM3 device models. Time integration is confirmed using simulation results in both time and frequency domains. The time integrator exhibits a clean spectrum without noticeable harmonics and consumes 0.25 mW with a gain of 15.48 dB at 20 MS/s.

This study presents an 8‐bit delay line digital‐to‐time converter (DTC) with pre‐skewing and digital time interpolation. Pre‐skewing that lowers the per‐stage‐delay of delay lines beyond that set by the chosen technology is investigated. A cascode tri‐state inverter is proposed to improve the isolation between the input and output of interpolation cells so as to improve the linearity of the time interpolator. Design considerations that critically affect the linearity of the DTC are examined in detail. The impact of the slope of the inputs of the time interpolator on the latency and linearity of the interpolator is analysed and the maximum slope of the input of interpolators yielding the minimum latency without sacrificing linearity, is obtained. The timing errors of DTC are investigated and the considerations of the layout of the DTC are examined. The DTC is designed in a TSMC 65 nm 1.0 V CMOS technology and analysed using Spectre with BSIM3V3 device models. Post‐layout simulation results show the DTC offers 3.6 ps resolution, 580 MS/s conversion rate, and consumes 383 μ W.

This letter presents a rotary travelling‐wave oscillator (RTWO) with reliable direction control in a standard 130 nm complementary metal–oxide–semiconductor (CMOS) technology. To achieve low phase noise (PN), and low power consumption, 16‐stages customised transmission line segments are designed and simulated on electromagnetic tools. The PN is investigated through modelling the RTWO as multiple standing‐wave oscillators. The proposed oscillator achieves 11.2% tuning range, 190.3 dBc/Hz figure‐of‐merit (FoM) at 1 MHz offset and 192.3 dBc/Hz FoM at 10 MHz offset with 5.8‐mW power consumption from 16‐GHz carrier.

Recently, integrated class DE amplifiers without matching networks have been proposed as a compact solution to drive piezoelectric ultrasound transducers for high-intensity focused ultrasound (HIFU) therapy. However, when driving a transducer array, it is not always possible to drive all transducers in ideal Class DE conditions due to variations in the impedance of each array element. This paper outlines a method to predict switching losses and to select good driving parameters for an entire array without using matching networks. To the best of the authors knowledge, this is the first paper to present such a method. The method is experimentally validated using an integrated driver developed by the authors.