Bootstrapped switches are extensively used in applications demanding high-speed and high-linearity sampling. Nevertheless, the mathematical analysis of distortions caused by parasitic effects has not been performed previously. This paper essentially analyzes three factors that affect the linearity of the switch: source-drain exchange, parasitic capacitive division, and charge redistribution. By employing the time-domain waveform integration technique along with Chebyshev polynomials, the Fourier series expression for on-resistance of the switch can be effectively elucidated. Consequently, the effects of all sources of distortion have been quantified individually. It has been found that both the on-resistance and the bootstrap capacitor has a quadratic effect (40 dB/dec) on the third-harmonic distortion of the sampled signals. A $1\times 9$ bootstrapped switch array has been fabricated using 180 nm technology to verify the proposed calculation model. Using the subsampling method, the measured total harmonic distortion (THD) performance was found to be highly consistent with the model calculation results, demonstrating the effectiveness and accuracy of the calculation model. The proposed calculation model will be highly beneficial for designers of bootstrapped switches.

Due to nonideal residue amplification, the limited resolution of pipelined analog-to-digital converters (ADCs) has become a popular research topic for ADC designers. High-gain and high-speed amplifiers usually consume too much power for a decent ADC. Hence, this paper proposes a fast and cost-effective foreground calibration strategy for cyclic-pipelined ADCs. The calibration strategy compensates for the gain error due to inter-stage residual amplification, which alleviates the DC gain requirement for internal amplifiers. Unlike other digital calibrations, the proposed scheme is implemented with a cyclic-pipelined structure, and only one parameter needs to be calibrated, whose value can be feasibly calculated by the Fix-Point Iteration algorithm. The proposed calibration scheme is implemented in an area-efficient 16-bit, 2 MS/s cyclic-pipelined ADC, fabricated in 180 nm CMOS technology. The ADC is designed and realized by cycling a 6-bit sub-ADC four times with 1-bit redundancy each time. The calibration algorithm manages to recover the sampled data to 93.85 dB spurious free dynamic range (SFDR) even with a 57.8 dB-DC-gain amplifier. The total power consumption of ADC is 17.92 mW and it occupies an active area of 1.8 mm².