Element matching approaches based on Optimal Combination Algorithms (OCAs) are methods that try to calibrate element mismatches in data converters by rearranging the mapping relations between circuit elements and control logics. This work for the first time proposes a universal method and its corresponding Figure-of-Merit to evaluate the performance of various OCA approaches. It adopts the quantile of integral nonlinearity as the criterion and is consequently compatible with most of matching OCAs. Dynamic performance and the corresponding effective-number-of-bits (ENOB) limited by mismatches are also investigated. A critical feature of the proposed method is its robustness to the disturbance of element standard deviation as long as the standard deviation is in a reasonable region. Merits of our method have been explained and proved mathematically, and also been verified numerically by data extracted from previously reported works and their reproduction by authors, which together make this proposal more convincing and rigorous. Due to those merits, our proposed method could also help designers to specify a feasible standard deviation for circuit elements when they are designing data converters with OCAs.

This paper presents a top-to-bottom element-matching strategy based on a full-permutation bisection algorithm for data converters. By bisecting the composing elements and recombining them for a minimal weight difference, the linearity of the data converter can be significantly improved. Three different approaches have been implemented for the proposed algorithm, and they are based on linear programming, stochastic quantization, and maximal linearly independent subset (MLIS) respectively. Their pros and cons have been discussed and simulated exhaustively, and all of them have been silicon proved via capacitive digital to analog converters in 180-nm technology. Measurement results of twenty dies for each approach verified the aforementioned theoretical analysis, and all three approaches could achieve sub-30 ppm for all codes after calibration. The worst integral nonlinearity at the most significant bit after calibration can be improved from 402 ppm to 10.9 ppm, which is equivalent to a 5.2-bit boost, indicating a promising potential of the proposed matching strategy. Besides, the MLIS-based approach is the first optimal-combination-algorithm-based matching strategy that achieves $\mathcal{O}(N)$ time complexity, as the authors know.

This work presents a 2-MS/s 18-bit successive-approximation-register analog-to-digital converter (ADC). Acapacitor digital-to-analog converter (CDAC) and a resistor digital-to-analog converter (RDAC) are cascaded to avoid the linearity limitation caused by parasitic capacitors on the bridge capacitor between the CDAC and the RDAC. An optimal-combination-algorithm (OCA)-based calibration is adopted to improve the linearity of the CDAC and the matching between CDAC and the bridge capacitor, and a least significant bit (LSB)-side dynamic element matching (DEM) strategy is applied to further improve the CDAC linearity. As for the RDAC, this work makes it calibration free by combining the parallel R-unit and R-2R topology. Measurement results show that the proposed ADC can achieve 91.4-dB signal-to-noise and distortion ratio (SNDR), 12.0-parts-per-million (ppm) (3.1-LSB) integral non-linearity (INL), and 174.0-dB FOM_S,SNDR (including the power consumed by the calibration logic), and the worst-case INL across 25 dies improves from 72.5ppm (19.0LSB) to 18.8ppm (4.9LSB) after the OCA-based calibration and theLSB-side DEM. To the best of the authors’ knowledge, this is the first high-precision (resolution $\geq 16$ bit) data converter adopting OCA-based calibration.

Due to nonideal residue amplification, the limited resolution of pipelined analog-to-digital converters (ADCs) has become a popular research topic for ADC designers. High-gain and high-speed amplifiers usually consume too much power for a decent ADC. Hence, this paper proposes a fast and cost-effective foreground calibration strategy for cyclic-pipelined ADCs. The calibration strategy compensates for the gain error due to inter-stage residual amplification, which alleviates the DC gain requirement for internal amplifiers. Unlike other digital calibrations, the proposed scheme is implemented with a cyclic-pipelined structure, and only one parameter needs to be calibrated, whose value can be feasibly calculated by the Fix-Point Iteration algorithm. The proposed calibration scheme is implemented in an area-efficient 16-bit, 2 MS/s cyclic-pipelined ADC, fabricated in 180 nm CMOS technology. The ADC is designed and realized by cycling a 6-bit sub-ADC four times with 1-bit redundancy each time. The calibration algorithm manages to recover the sampled data to 93.85 dB spurious free dynamic range (SFDR) even with a 57.8 dB-DC-gain amplifier. The total power consumption of ADC is 17.92 mW and it occupies an active area of 1.8 mm².

This paper introduces a capacitively coupled analog front-end featuring an adjustable high-pass cutoff frequency range of 7 mHz to 6.29 Hz. The DC operating point for the input differential pair is set by the dynamic equilibrium of the direct tunneling (DT) current. An output DC-servo loop (O-DSL), utilizing a duty-cycled operational transconductance amplifier (DC-OTA) together with a digital-assistant transconductance amplifier (DA-OTA), is designed at the main amplifier’s output nodes. By employing DC-OTA techniques in the O-DSL, an equivalent transconductance as low as 0.18 pA/V has been achieved, enabling the front-end to reach a 7 mHz high-pass cutoff frequency with a 6 pF on-chip integrating capacitor. A DA-OTA technique is used to widen the compensation range for low frequency interference. Additionally, a positive feedback capacitor in conjunction with a dual loop control mechanism is applied to enhance input impedance to 5.2 G$\Omega$ at 50 Hz within 30 ms calibration time. The front-end is fabricated in a standard 180 nm CMOS process, with a total current consumption of 3.01 $\mu$A and 6.37 NEF.

This article presents three techniques to improve the split-steering amplifier’s (SSA) performance and robustness. At the system level, differential-mode charge neutralization (DMCN) is introduced first to reset the circuit with minimum burden. Second, a DMCN-compatible common-mode feedforward (CMFF) strategy is introduced to reduce the impact of common-mode (CM) disturbance without introducing extra noise or sacrificing the bandwidth. The above two techniques are universal and can be applied in other pseudo-differential (PD) amplifier architectures. As for circuit implementation, two ring amplifiers (RAs) with different dead zones (DZs) are paralleled with the SSA to improve the slew rate (SR) of the overall amplifier. Dynamic bias adjustment is used to increase the response speed of the RAs and ensure that they will not be activated after slewing, which is critical to keep the overall amplifier low noise. The measured results demonstrate a $-$ 14.2-dB CM-CM gain and 11.7 times SR boosting. The measured noise efficiency factor (NEF) is 2.30, and $\overline{V_{n}^2} \cdot I_{\rm supply}$ is 1.49 times overperforming previous works.