In this work, ISFET frontends utilising the direct tunneling current to eliminate trapped charge are proposed. The principle has been investigated and verified via silicon-imitated ISFET first, where silicon capacitors are used to imitate the passivation ones. Because the dominant tunneling components depend on the potential difference between Gate and Drain terminals, a source-follower structure could itself perform a highpass filter with time constant at 10–100 seconds level. Additionally, a time-constant regulation mechanism is presented by feeding the output signal back to the drain terminal of ISFETs, achieving a regulation factor over 50, namely from 4.7 seconds to 243.4 seconds in our implementation. Afterwards in chemical test, proposed ISFETs have been verified in terms of unit passivation capacitance, linearity, noise and sensitivity for ISFETs with 3 different top metal areas. It is found that approximately 30.12 mV/pH sensitivity can be achieved, and for the first time we managed to derive the relation between chemical flicker noise and sensing metal area.

Automatic transistor sizing in circuit design continues to be a formidable challenge. Despite that Bayesian optimization (BO) has achieved significant success, it is circuit-specific, limiting the accumulation and transfer of design knowledge for broader applications. This paper proposes (1) efficient automatic kernel construction, (2) the first transfer learning across different circuits and technology nodes for BO, and (3) a selective transfer learning scheme to ensure only useful knowledge is utilized. These three novel components are integrated into BO with Multi-objective Acquisition Ensemble (MACE) to form Knowledge Alignment and Transfer Optimization (KATO) to deliver state-of-the-art performance: up to 2x simulation reduction and 1.2x design improvement over the baselines.

Element matching approaches based on Optimal Combination Algorithms (OCAs) are methods that try to calibrate element mismatches in data converters by rearranging the mapping relations between circuit elements and control logics. This work for the first time proposes a universal method and its corresponding Figure-of-Merit to evaluate the performance of various OCA approaches. It adopts the quantile of integral nonlinearity as the criterion and is consequently compatible with most of matching OCAs. Dynamic performance and the corresponding effective-number-of-bits (ENOB) limited by mismatches are also investigated. A critical feature of the proposed method is its robustness to the disturbance of element standard deviation as long as the standard deviation is in a reasonable region. Merits of our method have been explained and proved mathematically, and also been verified numerically by data extracted from previously reported works and their reproduction by authors, which together make this proposal more convincing and rigorous. Due to those merits, our proposed method could also help designers to specify a feasible standard deviation for circuit elements when they are designing data converters with OCAs.

Bootstrapped switches are extensively used in applications demanding high-speed and high-linearity sampling. Nevertheless, the mathematical analysis of distortions caused by parasitic effects has not been performed previously. This paper essentially analyzes three factors that affect the linearity of the switch: source-drain exchange, parasitic capacitive division, and charge redistribution. By employing the time-domain waveform integration technique along with Chebyshev polynomials, the Fourier series expression for on-resistance of the switch can be effectively elucidated. Consequently, the effects of all sources of distortion have been quantified individually. It has been found that both the on-resistance and the bootstrap capacitor has a quadratic effect (40 dB/dec) on the third-harmonic distortion of the sampled signals. A $1\times 9$ bootstrapped switch array has been fabricated using 180 nm technology to verify the proposed calculation model. Using the subsampling method, the measured total harmonic distortion (THD) performance was found to be highly consistent with the model calculation results, demonstrating the effectiveness and accuracy of the calculation model. The proposed calculation model will be highly beneficial for designers of bootstrapped switches.

In this paper, a wireless power transfer (WPT) system composed of a voltage-mode fully integrated resonance regulating rectifier (IR ³ ) and an on-chip antenna running at 402 MHz has been designed for bioimplants in deep tissue. The proposed IR ³ , including a 200 pF decoupling capacitor, is implemented in a 0.22 mm ² active area in the 180-nm CMOS process. A charging duration based regulation compensation circuit offers a low ripple factor of 0.3% at a 1.8 V output voltage and a high voltage conversion efficiency (VCE) of 1.73 to overcome the low inductive coupling coefficient (under 0.01) due to the deep implant scenario. And a clock gating VCDL-based on-&-off delay compensation scheme is proposed to compensate for the phase error of the IR ³ . Performing rectification and regulation simultaneously in a single stage, the IR ³ effectively enhances power conversion efficiency. The whole system achieves a power conversion efficiency (PCE) of 65% with a 1.5 mW load. In addition, digital control-based compensation circuits also improve its transient response performance, the 1% setting time is only 6.9 μs when the load changes from 65 μW to 1.5 mW.

This paper presents a top-to-bottom element-matching strategy based on a full-permutation bisection algorithm for data converters. By bisecting the composing elements and recombining them for a minimal weight difference, the linearity of the data converter can be significantly improved. Three different approaches have been implemented for the proposed algorithm, and they are based on linear programming, stochastic quantization, and maximal linearly independent subset (MLIS) respectively. Their pros and cons have been discussed and simulated exhaustively, and all of them have been silicon proved via capacitive digital to analog converters in 180-nm technology. Measurement results of twenty dies for each approach verified the aforementioned theoretical analysis, and all three approaches could achieve sub-30 ppm for all codes after calibration. The worst integral nonlinearity at the most significant bit after calibration can be improved from 402 ppm to 10.9 ppm, which is equivalent to a 5.2-bit boost, indicating a promising potential of the proposed matching strategy. Besides, the MLIS-based approach is the first optimal-combination-algorithm-based matching strategy that achieves $\mathcal{O}(N)$ time complexity, as the authors know.