Jaehyun Park

Prof. Jaehyun Park

orcid

Research Focus & Metrics

Academic Career Length

8Years (2019-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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30 January 2020 in Sensors
Verified
Journal Article
Open access
PDF file
JPJaehyun Park
Jaehyun Park
GBGanapati Bhat
Ganapati Bhat
ANAnish NK
Anish NK
CGCemil Geyik
Cemil Geyik
UOUmit Ogras
Umit Ogras
Hyung Gyu LeeHyung Gyu Lee
Hyung Gyu Lee
Wearable internet of things (IoT) devices can enable a variety of biomedical applications, such as gesture recognition, health monitoring, and human activity tracking. Size and weight constraints limit the battery capacity, which leads to frequent charging requirements and user dissatisfaction. Minimizing the energy consumption not only alleviates this problem, but also paves the way for self-powered devices that operate on harvested energy. This paper considers an energy-optimal gesture recognition application that runs on energy-harvesting devices. We first formulate an optimization problem for maximizing the number of recognized gestures when energy budget and accuracy constraints are given. Next, we derive an analytical energy model from the power consumption measurements using a wearable IoT device prototype. Then, we prove that maximizing the number of recognized gestures is equivalent to minimizing the duration of gesture recognition. Finally, we utilize this result to construct an optimization technique that maximizes the number of gestures recognized under the energy budget constraints while satisfying the recognition accuracy requirements. Our extensive evaluations demonstrate that the proposed analytical model is valid for wearable IoT applications, and the optimization approach increases the number of recognized gestures by up to 2.4× compared to a manual optimization.

10 November 2025 in ACM Transactions on Design Automation of Electronic Systems
Verified
Journal Article
Open access
LPLukas Pfromm
Lukas Pfromm
AKAlish Kanani
Alish Kanani
HSHarsh Sharma
Harsh Sharma
PSParth Solanki
Parth Solanki
ETEric Tervo
Eric Tervo
UOUmit Ogras
Umit Ogras
Rapidly evolving artificial intelligence and machine learning applications require ever-increasing computational capabilities, while monolithic 2D design technologies approach their limits. 2.5D/3D heterogeneous integration of smaller chiplets using advanced packaging has emerged as a promising paradigm for addressing this limit and meeting performance demands. These approaches offer a significant cost reduction and higher manufacturing yield than monolithic 2D integrated circuits. However, the compact arrangement and high compute density of these systems exacerbate thermal management challenges, potentially compromising performance. Addressing these thermal modeling challenges is critical, especially as system sizes grow and different design stages require varying levels of accuracy and speed. Since no single thermal modeling technique meets all these needs, this article introduces MFIT, a range of multi-fidelity thermal models that effectively balance accuracy and speed. These multi-fidelity models can enable efficient design space exploration and runtime thermal management. Our extensive testing on systems with 16, 36, and 64 2.5D integrated chiplets and 16×3 3D integrated chiplets demonstrates that these models can reduce execution times from days to mere seconds and milliseconds with negligible loss in accuracy.

19 June 2020 in Energies
Verified
Journal Article
Open access
PDF file
YCYoung Hoo Cho
Young Hoo Cho
JPJaehyun Park
Jaehyun Park
NCNaehyuck Chang
Naehyuck Chang
JKJaemin Kim
Jaemin Kim
A thermoelectric generator (TEG) is a clean electricity generator from a heat source, usually waste heat. However, it is not as widely utilized as other electricity generators due to low conversion efficiency from heat to electricity. One approach is a system-level net power optimization for a TEG system composed of TEGs, heat sink, and fans. In this paper, we propose airflow reuse after cooling preceding TEGs to maximize system net power. For the accurate system net power, we model the TEG system, air, and heat source with proper dimension and material characteristics, and simulate with a computational fluid dynamics program. Next, the TEG power generation and the fan power consumption are calculated in consideration of the Seebeck coefficient and internal electrical resistance varying with hot and cold side temperatures. Finally, we find the optimal number of TEGs and fan speed generating the most efficient system net power in various TEG systems. The results show that the system with a side fan with a specific number of TEGs provides a system net power up to 58.6% higher than when with a top fan. The most efficient system net power with the side fan increases up to four TEGs generating 1.907 W at 13,000 RPM.

20 August 2021 in IEEE Internet of Things Journal
Verified
Journal Article
Closed access
Yigit TuncelYigit Tuncel
Yigit Tuncel
GBGanapati Bhat
Ganapati Bhat
JPJaehyun Park
Jaehyun Park
UOUmit Ogras
Umit Ogras
Energy harvesting offers an attractive and promising mechanism to power low-energy devices. However, it alone is insufficient to enable an energy-neutral operation, which can eliminate tedious battery charging and replacement requirements. Achieving an energy-neutral operation is challenging since the uncertainties in harvested energy undermine the quality of service requirements. To address this challenge, we present a runtime energy-allocation framework that optimizes the utility of the target device under energy constraints using a rollout algorithm, which is a sequential approach to solve dynamic optimization problems. The proposed framework uses an efficient iterative algorithm to compute initial energy allocations at the beginning of a day. The initial allocations are then corrected at every interval to compensate for the deviations from the expected energy harvesting pattern. We evaluate this framework using solar and motion energy harvesting modalities and American Time Use Survey data from 4772 different users. Compared to prior techniques, the proposed framework achieves up to 35% higher utility even under energy-limited scenarios. Moreover, measurements on a wearable device prototype show that the proposed framework has $1000\times $ smaller energy overhead than iterative approaches with a negligible loss in utility.

26 September 2025 in ACM Transactions on Embedded Computing Systems
Verified
Journal Article
Open access
JKJiyong Kim
Jiyong Kim
JLJaeho Lee
Jaeho Lee
JLJiahao Lin
Jiahao Lin
AKAlish Kanani
Alish Kanani
MSMiao Sun
Miao Sun
JPJaehyun Park
Jaehyun Park
State Space Model (SSM)-based machine learning architectures have recently gained significant attention for processing sequential data. Mamba, a recent sequence-to-sequence SSM, offers competitive accuracy with superior computational efficiency compared to state-of-the-art transformer models. While this advantage makes Mamba particularly promising for resource-constrained edge devices, no hardware acceleration frameworks are currently optimized for deploying it in such environments. This article presents eMamba, a comprehensive end-to-end hardware acceleration framework explicitly designed for deploying Mamba models on edge platforms. eMamba maximizes computational efficiency by replacing complex normalization layers with lightweight hardware-aware alternatives and approximating expensive operations, such as SiLU activation and exponentiation, considering the target applications. Then, it performs an approximation-aware neural architecture search (NAS) to tune the learnable parameters used during approximation. Evaluations with Fashion-MNIST, CIFAR-10, and MARS, an open-source human pose estimation dataset, show eMamba achieves comparable accuracy to state-of-the-art techniques using 1.63–19.9× fewer parameters. In addition, it generalizes well to large-scale natural language tasks, demonstrating stable perplexity across varying sequence lengths on the WikiText2 dataset. We also quantize and implement the entire eMamba pipeline on an AMD ZCU102 FPGA and ASIC using GlobalFoundries (GF) 22 nm technology. Experimental results show 4.95–5.62× lower latency and 2.22–9.95× higher throughput, with 4.77× smaller area, 9.84× lower power, and 48.6× lower energy consumption than baseline solutions while maintaining competitive accuracy.

1 November 2020 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verified
Journal Article
Closed access
YLYongwoo Lee
Yongwoo Lee
JPJaehyun Park
Jaehyun Park
JRJunhee Ryu
Junhee Ryu
YKYounghyun Kim
Younghyun Kim