This article addresses the growing need in resource-constrained edge computing scenarios for energy-efficient convolutional neural network (CNN) accelerators on mobile Field-Programmable Gate Array (FPGA) systems. In particular, we concentrate on register transfer level (RTL) design flow optimization to improve programming speed and power efficiency. We present a re-configurable accelerator design optimized for CNN-based object-detection applications, especially suitable for mobile FPGA platforms like the Xilinx PYNQ-Z2. By not only optimizing the MAC module using Enhanced clock gating (ECG), the accelerator can also use low-power techniques such as Local explicit clock gating (LECG) and Local explicit clock enable (LECE) in memory modules to efficiently minimize data access and memory utilization. The evaluation using ResNet-20 trained on the CIFAR-10 dataset demonstrated significant improvements in power efficiency consumption (up to 22%) and performance. The findings highlight the importance of using different optimization techniques across multiple hardware modules to achieve better results in real-world applications.

In resource-constrained edge environments—such as mobile devices, IoT systems, and electric vehicles—energy-efficient Convolution Neural Network (CNN) accelerators on mobile Field Programmable Gate Arrays (FPGAs) are gaining significant attention for real-time object detection tasks. This paper presents a low-power implementation of the Tiny YOLOv4 object detection model on the Xilinx ZCU104 FPGA platform by using Register Transfer Level (RTL) optimization techniques. We proposed three RTL techniques in the paper: (i) Local Explicit Clock Enable (LECE), (ii) operand isolation, and (iii) Enhanced Clock Gating (ECG). A novel low-power design of Multiply-Accumulate (MAC) operations, which is one of the main components in the AI algorithm, was proposed to eliminate redundant signal switching activities. The Tiny YOLOv4 model, trained on the COCO dataset, was quantized and compiled using the Tensil tool-chain for fixed-point inference deployment. Post-implementation evaluation using Vivado 2022.2 demonstrates around 29.4% reduction in total on-chip power. Our design supports real-time detection throughput while maintaining high accuracy, making it ideal for deployment in battery-constrained environments such as drones, surveillance systems, and autonomous vehicles. These results highlight the effectiveness of RTL-level power optimization for scalable and sustainable edge AI deployment.

The growing demand for energy-efficient memory systems in artificial intelligence (AI) accelerators has intensified research into novel device technologies and computing-in-memory (CIM) architectures. While conventional binary SRAM architectures using CMOS and FinFET devices have been widely explored, ternary-based designs offer potential benefits in terms of storage density and computational efficiency. This work presents a low-power analysis of a sense-amplifier embedded (SE) 9-transistor (9T) ternary SRAM architecture implemented using Carbon Nanotube Field-Effect Transistors (CNFETs) and Gate-All-Around Field-Effect Transistors (GAAFETs). The comparative results show a substantial reduction in total power consumption—from 109.2 $\mathsf{\mu }$W in FinFET to 26.73 $\mathsf{\mu }$W in GAAFET—and an ultra-low power of only 0.0004 $\mathsf{\mu }$W in CNFET, representing a 99% reduction compared to FinFET designs. Similarly, the total delay decreases from 0.01108 ns in FinFET to 0.004 ns in GAAFET, while the CNFET design shows a modest delay of 0.017 ns. Overall, GAAFET offers the best trade-off between power and delay, whereas CNFET achieves the lowest power consumption, making it highly suitable for ultra-low-power AI applications. These findings emphasize the superior energy efficiency and scalability potential of CNFET- and GAAFET-based designs over traditional FinFETs, offering a promising pathway toward next-generation ternary CIM-enabled SRAM architectures. Furthermore, fabrication challenges related to CNFET and GAAFET technologies are discussed, providing insights into their practical feasibility for large-scale integration.