This article addresses the growing need in resource-constrained edge computing scenarios for energy-efficient convolutional neural network (CNN) accelerators on mobile Field-Programmable Gate Array (FPGA) systems. In particular, we concentrate on register transfer level (RTL) design flow optimization to improve programming speed and power efficiency. We present a re-configurable accelerator design optimized for CNN-based object-detection applications, especially suitable for mobile FPGA platforms like the Xilinx PYNQ-Z2. By not only optimizing the MAC module using Enhanced clock gating (ECG), the accelerator can also use low-power techniques such as Local explicit clock gating (LECG) and Local explicit clock enable (LECE) in memory modules to efficiently minimize data access and memory utilization. The evaluation using ResNet-20 trained on the CIFAR-10 dataset demonstrated significant improvements in power efficiency consumption (up to 22%) and performance. The findings highlight the importance of using different optimization techniques across multiple hardware modules to achieve better results in real-world applications.

In resource-constrained edge environments—such as mobile devices, IoT systems, and electric vehicles—energy-efficient Convolution Neural Network (CNN) accelerators on mobile Field Programmable Gate Arrays (FPGAs) are gaining significant attention for real-time object detection tasks. This paper presents a low-power implementation of the Tiny YOLOv4 object detection model on the Xilinx ZCU104 FPGA platform by using Register Transfer Level (RTL) optimization techniques. We proposed three RTL techniques in the paper: (i) Local Explicit Clock Enable (LECE), (ii) operand isolation, and (iii) Enhanced Clock Gating (ECG). A novel low-power design of Multiply-Accumulate (MAC) operations, which is one of the main components in the AI algorithm, was proposed to eliminate redundant signal switching activities. The Tiny YOLOv4 model, trained on the COCO dataset, was quantized and compiled using the Tensil tool-chain for fixed-point inference deployment. Post-implementation evaluation using Vivado 2022.2 demonstrates around 29.4% reduction in total on-chip power. Our design supports real-time detection throughput while maintaining high accuracy, making it ideal for deployment in battery-constrained environments such as drones, surveillance systems, and autonomous vehicles. These results highlight the effectiveness of RTL-level power optimization for scalable and sustainable edge AI deployment.

Deploying deep neural networks on edge devices such as embedded GPUs and FPGAs remains challenging due to high computational cost, memory footprint, and sensitivity to class imbalance. Existing compression techniques, including knowledge distillation, often overlook hardware constraints and minority-class performance, leading to suboptimal real-world deployment. This article introduces CB-DistillGrad, a unified hardware-aware distillation framework that jointly optimizes accuracy, model compactness, and deployment efficiency. The proposed system integrates: (1) a lightweight student architecture built with depthwise separable convolutions, squeeze-and-excitation attention, progressive dropout, and hardware-friendly Hard Swish activation; (2) a CB-Distill Loss that couples class-balanced focal loss with reweighted Kullback–Leibler divergence to mitigate teacher bias and improve minority-class accuracy; and (3) gradient conflict resolution via PCGrad to stabilize optimization under multi-objective supervision. The resulting student network achieves 87.11% overall accuracy on the RSCD road-surface dataset using only 130K parameters (0.52 MB at FP32), a 96.8% reduction compared to the 4.1M-parameter teacher. On the NVIDIA GPU, inference occurs at 1.05 ms/image (949 FPS) with 72Wpower, 2.15× faster than the teacher. On the NVIDIA Jetson AGX Orin, inference occurs at 11.70 ms/image (85 FPS) with 7.36 W power, achieving 2.8× speedup and 4.5× energy reduction. On the Xilinx ZCU104 FPGA, inference occurs at 62.19 ms/image (16 FPS) with 4.42Wpower, demonstrating a 27× energy reduction compared to GPU execution. These results demonstrate a practical framework for training and deploying compact, class-balanced, and hardware-optimized deep learning models on resource-constrained platforms.

The increasing demand for high-performance and low-power hardware in artificial intelligence (AI) applications, such as speech recognition, facial recognition, and object detection, has driven the exploration of advanced memory designs. Convolutional neural networks (CNNs) and deep neural networks (DNNs) require intensive computational resources, leading to memory access times and power consumption challenges. To address these challenges, we propose the application of computing-in-memory (CIM) within FinFET-based 8T SRAM structures, specifically utilizing P-latch N-access (PLNA) and single-ended (SE) configurations. Our design significantly reduces power consumption by up to 56% in the PLNA configuration and 60% in the SEconfiguration compared to traditional FinFET SRAM designs. These reductions are achieved while maintaining competitive delay performance, making our approach a promising solution for implementing efficient and low-power AI hardware. Detailed simulations in 7 nm FinFET technology underscore the potential of these CIM-based SRAM structures in overcoming the computational bottlenecks associated with DNNs and CNNs.

The increasing demand for high-performance and low-power hardware in artificial intelligence (AI) applications—such as speech recognition, facial recognition, and object detection—has driven the exploration of advanced memory designs. Convolutional neural networks (CNNs) and deep neural networks (DNNs) require intensive computational resources, leading to significant challenges in terms of memory access time and power consumption. Compute-in-Memory (CIM) architectures have emerged as an alternative by executing computations directly within memory arrays, thereby reducing the expensive data transfer between memory and processor units. In this work, we present a 6T SRAM-based CIM architecture implemented using FinFET technology, aiming to reduce both power consumption and access delay. We explore and simulate three different SRAM cell structures—PLNA (P-Latch N-Access), NLPA (N-Latch P-Access), and SE (Single-Ended)—to assess their suitability for CIM operations. Compared to a reference 10T XNOR-based CIM design, our results show that the proposed structures achieve an average power consumption approximately 70% lower, along with significant delay reduction, without compromising functional integrity. A comparative analysis is presented to highlight the trade-offs between the three configurations, providing insights into their potential applications in low-power AI accelerator design.

Edge AI platforms — autonomous drones, smart cameras, and IoT devices — demand real-time deep learning inference under tight energy and latency budgets. Field-Programmable Gate Arrays (FPGAs) are widely deployed as inference accelerators owing to their reconfigurable logic fabric, yet high switching activity in Multiply–Accumulate (MAC) units remains the dominant source of dynamic power, limiting deployment on power-sensitive embedded systems. We present a MAC-centric register-transfer level (RTL) power-optimization methodology integrating six complementary techniques: register banking with change-detect enables, quantization-aware operand gating, enable-based frequency throttling, pipeline valid-gating, dynamic precision scaling, and grouped bank updates with conditional upper-bit freezing. Applied simultaneously across the full MAC datapath of a Tiny-YOLOv4 object-detection accelerator on the Xilinx ZCU104 FPGA, these techniques suppress unnecessary signal transitions and minimize idle switching without modifying network topology, weight values, or numerical precision. Experimental results demonstrate a 59.2% reduction in dynamic power and a 51.4% reduction in total on-chip power, with energy per inference frame improving by 59.2% at 9.87 FPS. Detection accuracy is preserved by construction — the optimized implementation produces bit-exact outputs identical to the baseline Tensil implementation across 595 live inference frames. On-board validation using ZCU104 INA226 current sensors confirms a 62.5% reduction in inference-induced switching power, consistent with Vivado simulation estimates to within one percentage point. Timing closure is maintained at 200 MHz with zero negative slack. The primary resource cost is increased LUT utilization (25% → 57%), reflecting the control logic overhead of the six techniques.