The increasing demand for high-performance and low-power hardware in artificial intelligence (AI) applications—such as speech recognition, facial recognition, and object detection—has driven the exploration of advanced memory designs. Convolutional neural networks (CNNs) and deep neural networks (DNNs) require intensive computational resources, leading to significant challenges in terms of memory access time and power consumption. Compute-in-Memory (CIM) architectures have emerged as an alternative by executing computations directly within memory arrays, thereby reducing the expensive data transfer between memory and processor units. In this work, we present a 6T SRAM-based CIM architecture implemented using FinFET technology, aiming to reduce both power consumption and access delay. We explore and simulate three different SRAM cell structures—PLNA (P-Latch N-Access), NLPA (N-Latch P-Access), and SE (Single-Ended)—to assess their suitability for CIM operations. Compared to a reference 10T XNOR-based CIM design, our results show that the proposed structures achieve an average power consumption approximately 70% lower, along with significant delay reduction, without compromising functional integrity. A comparative analysis is presented to highlight the trade-offs between the three configurations, providing insights into their potential applications in low-power AI accelerator design.

The increasing computational demands of deep neural network inference drive the need for energy-efficient hardware accelerators that minimize data movement between memory and processing units. Compute-in-memory (CIM) architectures address this bottleneck by embedding computation directly within memory arrays, reducing the overhead of repeated weight transfers in conventional von Neumann systems. Conventional 6T SRAM-based digital CIM bitcells incur significant transistor overhead as arrays scale, motivating exploration of reduced-transistor bitcell alternatives. We propose a compact 4T+2T SRAM-based digital CIM bitcell implemented in 45 nm CMOS, combining a 4T SRAM storage cell with a 2T multiplier for bitwise multiply-and-accumulate (MAC) operations. The proposed design reduces transistor count from 8 to 6 compared to the 6T+2T reference, lowering parasitic capacitance and hardware overhead without compromising memory or computation functionality. Transient simulations confirm correct write, read, and CIM operations. The bitcell achieves a read delay of 26.91 ps, read power of 1.351 nW, and read energy of 0.005403 fJ—reductions of 98.7%, 86.5%, and 73.1% over the 6T+2T reference, respectively. For CIM operation, bitwise multiplication power decreases from 1.772 µW to 0.8014 µW and energy from 10.63 fJ to 4.808 fJ, representing a 54.8% reduction in both metrics, with only a marginal CIM delay increase of 3.13 ps. Monte Carlo analysis across 100 samples confirms robust write behavior under process variation, with write delay ranging from 55.02 to 69.59 ps and write energy from 0.05870 to 0.06557 fJ. Static noise margin analysis yields an SNM of 83.7 mV under nominal conditions, confirming stable data retention. These results demonstrate that the proposed 4T+2T bitcell offers strong transistor efficiency, energy savings, and computational correctness, making it a promising candidate for area-efficient digital CIM architectures targeting edge AI inference.

The growing demand for energy-efficient memory systems in artificial intelligence (AI) accelerators has intensified research into novel device technologies and computing-in-memory (CIM) architectures. While conventional binary SRAM architectures using CMOS and FinFET devices have been widely explored, ternary-based designs offer potential benefits in terms of storage density and computational efficiency. This work presents a low-power analysis of a sense-amplifier embedded (SE) 9-transistor (9T) ternary SRAM architecture implemented using Carbon Nanotube Field-Effect Transistors (CNFETs) and Gate-All-Around Field-Effect Transistors (GAAFETs). The comparative results show a substantial reduction in total power consumption—from 109.2 $\mathsf{\mu }$W in FinFET to 26.73 $\mathsf{\mu }$W in GAAFET—and an ultra-low power of only 0.0004 $\mathsf{\mu }$W in CNFET, representing a 99% reduction compared to FinFET designs. Similarly, the total delay decreases from 0.01108 ns in FinFET to 0.004 ns in GAAFET, while the CNFET design shows a modest delay of 0.017 ns. Overall, GAAFET offers the best trade-off between power and delay, whereas CNFET achieves the lowest power consumption, making it highly suitable for ultra-low-power AI applications. These findings emphasize the superior energy efficiency and scalability potential of CNFET- and GAAFET-based designs over traditional FinFETs, offering a promising pathway toward next-generation ternary CIM-enabled SRAM architectures. Furthermore, fabrication challenges related to CNFET and GAAFET technologies are discussed, providing insights into their practical feasibility for large-scale integration.