This article presents a low-power 256-element $Ka$ -band CMOS phased-array receiver utilizing on-chip distributed radiation sensors for the low Earth orbit (LEO) small satellite communication system. Since the available solar cell area limits the power generation of the small LEO satellites, a distributed current-sharing common-gate (CG) low noise amplifier (LNA) and a voltage-tuning variable gain amplifier (VGA) are introduced to reduce power consumption. After utilizing the proposed technique, the power consumption of the beamformer is 2.95 mW/element. Moreover, the proposed voltage-tuning VGA is configured to utilize both upper and lower transistors for gain contributions to save power. The on-chip distributed radiation sensors are presented to eliminate the non-uniform radiation influence and realize 0.22-dB/Mrad gain degradation performance. The proposed receiver achieves $-$ 20-dBm single-element IIP3 with a 3.6-dB noise figure. The occupied on-chip area for a single element is only 0.24 mm $^2$ . DVB-S2X standard modulated signals of up to 256 amplitude and phase-shift keying (APSK) can be supported in the over-the-air (OTA) measurement. The receiver achieves $-$ 31.3-dB EVM and 24-Gb/s link speed under 1.5-GBaud dual-linear polarization signals. The measured 256-element beam pattern can cover radiated angle from $-$ 50 $^\circ$ to $+$ 50 $^\circ$ with lower than $-$ 9-dBc sidelobe level. Thanks to the proposed low-power distributed current-sharing CG LNA and on-chip radiation sensors, a low-power radiation-hardened phased-array receiver can be achieved for the small LEO satellites.
4 January 2023 in IEEE Journal of Solid-State Circuits
This article demonstrates a 39-GHz CMOS phased-array beamformer aiming for power-efficient and area-efficient fifth-generation (5G) dual-polarized multiple-in–multiple-out (DP-MIMO) applications. To address the digital pre-distortion (DPD) implementation issue in the massive beamformer elements with Doherty technique integrated, an inter-element mismatch compensation technique is introduced for improving the shared-lookup table (LUT) DPD performance over the process, voltage and temperature (PVT) variations. A bidirectional Doherty power amplifier (PA)-LNA is proposed to enhance the power back-off (PBO) efficiency regarding the high peak-to-average power ratio (PAPR) 5G signals, meanwhile cost down the system by the unbalanced neutralized bidirectional operation. The proposed phased-array beamformer chip is fabricated in 65-nm CMOS technology and packaged in a wafer-level chip-scale package (WLCSP). Each element occupies only a 0.82-mm2 chip area, including the on-chip low-dropout regulator (LDO). The measured stand-alone Doherty PA-LNA achieves 18.9-dBm saturated output power with 17.8% power-added efficiency (PAE) at 6-dB PBO in PA mode and obtains a 4.8-dB noise figure (NF) at 40 GHz in LNA mode. By utilizing the proposed mismatch compensation, the measured 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiple access (OFDMA)-mode error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) with the shared-LUT DPD are improved from −22.4 to −25.0 dB and from −28.7 to −32.1 dBc, respectively. The 64-element module achieves a 55.2-dBm saturated effective isotropic radiated power (EIRP) and supports 21-Gb/s single-carrier (SC) mode data streaming. The measured 64-element transmitter (TX) EVM is −25.2 dB at 43.2 dBm with 3.5-GSymbol/s baud rate in 64 QAM, and the corresponding 64-to-4 elements TX-to-receiver (RX) EVM is −22.5 dB. The consumed power for each element is 402 mW at saturation output point in TX mode and 87 mW in RX mode.
19 October 2022 in IEEE Journal of Solid-State Circuits
This article introduces a power-efficient 24.25– 71-GHz multi-band phased-array receiver supporting all allocated fifth-generation mobile network new radio (5G NR) frequency range 2 (FR2) bands at 24/28/39/47 GHz and the potential 5G NR-U bands in unlicensed 57–71 GHz. A novel harmonic-selection technique is introduced to extend the operating bandwidth with low power consumption. By switching between the fundamental-selected mode, the second-harmonic-selected mode, and the third-harmonic-selected mode, only signals in the desired bands can be preserved, while the unselected mixing components are rejected. A dual-mode multi-band low-noise amplifier (LNA) based on a configurable transformer is adopted to realize broadband operation with minimized power consumption and noise figure (NF). The Hartley architecture is employed to further improve the image rejection performance. A hybrid-type polyphase filter (PPF) with a detector-based high-precision calibration block is utilized in this work to realize the Hartley operation with reduced insertion loss (IL). The proposed phased-array receiver is fabricated in a standard 65-nm bulk CMOS process. With the concerted efforts of all components, the proposed multi-band receiver can support 5G standard-compliant OFDMA-mode modulated signals up to 256QAM with a 400-MHz channel bandwidth from 24 to 71 GHz. Better than 36-dB inter-band blocker rejections can be maintained by this work. With existing of 0-dBc inter-band blockers at worst case frequencies, this receiver shows EVMs of $-$ 33.3, $-$ 30.9, $-$ 31.6, and $-$ 28.5 dB at 28, 39, 47.2, and 60.1 GHz, respectively. The power consumptions for a single receiver channel are 36, 32, 51, and 71 mW at 28, 39, 47.2, and 60.1 GHz, respectively.
19 December 2024 in IEEE Journal of Solid-State Circuits
This work presents a D-band (110–170 GHz) CMOS transceiver (TRX) chipset that covers a 56-GHz (114–170 GHz) signal-chain bandwidth. Both the transmitter (TX) and the receiver (RX) operate as heterodyne architectures with external intermediate frequency (IF) and local oscillator (LO) signals. An eight-way low- Q power-combined power amplifier (PA), a two-way low- Q power-combined low-noise amplifier (LNA), wideband-impedance-transformation passive mixers, common-source-based cascaded distributed amplifiers (DAs), and a low-loss wideband chip-to-waveguide printed circuit board (PCB) transition are proposed with improved bandwidth and linearity to support high-order wideband quadrature amplitude modulation (QAM) signals. The TRX chipset was fabricated using a 65-nm CMOS process. The TX achieves a 13-dBm saturated output power at 130 GHz with 1150-mW dc power. The RX achieves a 12-dB noise figure (NF) with 550-mW dc power. The proposed TRX chipset achieves a data rate of 200 Gb/s by 32QAM in the single-input–single-output (SISO) over-the-air (OTA) measurement at 0.32 m. A data rate of 150 Gb/s by 16QAM is realized with 43-dBi antennas at 15 m. Additionally, a 640-Gb/s 4 $\times$ 4 OTA line-of-sight multiinput multioutput (LOS-MIMO) is demonstrated at 0.52 m.
14 September 2023 in IEEE Journal of Solid-State Circuits
This article introduces a low-power radiation-hardened $Ka$ -band CMOS phased-array receiver for the low Earth orbit (LEO) small satellite communication system. As the available solar panel area limits the power consumption of the receiver, a multi-coupling common-gate (CG) low noise amplifier (LNA) with current-sharing topology and built-in 180 $^\circ$ phase shifter is proposed in this work to solve the power issue. The multi-coupling LNA utilizes three coupling inductors to reduce the input matching impedance with a smaller input CMOS transistor size. After implementing the proposed technique, a single beamformer realized a 3.4-mW typical power consumption compared with the conventional works with 17.3–195-mW power consumption. The receiver with magnetic-tuning phase shifter (MTPS) has 0.06-dB/Mrad gain and 0.4 $^\circ$ /Mrad phase degradations and is the lowest reported root-mean-square phase and gain errors due to radiation. The proposed receiver achieves $-$ 22-dBm IIP3 with a 3.8-dB noise figure. The required on-chip area for each element is only 0.2 mm $^2$ . In the over-the-air (OTA) measurement, digital video broadcasting-second generation extension (DVB-S2x) standard modulated signals of up to 256 amplitude phase shift keying (APSK) can be supported by the proposed large array modules. This work realizes $-$ 33.2-dB error vector magnitude (EVM) and 12.8-Gb/s link speed with 1.6-GHz channel bandwidth. The measured beam pattern can cover radiated angle from $-$ 50 $^\circ$ to $+$ 50 $^\circ$ with lower than $-$ 10-dBc sidelobe level. Because of the proposed multi-coupling LNA and MTPS, a low-power radiation-hardened phased-array receiver for small LEO satellites can be achieved in this work.
1 May 2023 in IEEE Microwave and Wireless Technology Letters
A $Ka$ -band 64-element deployable active phased-array transmitter (TX) on a hetero segment liquid crystal polymer (LCP) substrate for small satellites is proposed. The proposed phased-array TX achieved a large array size implementation and a small form factor with integrated six-layer and two-layer LCP substrates. Antenna and transmission line designs considering hetero layer structure are presented in detail. Achieving 46.7 dBm electronically isotropically radiated power (EIRP), the proposed phased-array TX can support 256-APSK DVB-S2X. As a result, the proposed deployable active phased-array TX successfully realizes low-launch cost with a 9.65 g lightweight and large antenna aperture size with superior EVM performance.