With countless applications, time measurements are among industrial electronics' current most important challenges. This is not a matter of precision, which by now standard architectures have brought in the order of picoseconds and therefore at the physical limits of most common detection systems, but to the number of channels in continuous enormous growth. Just think about time-of-flight (TOF)-based applications like 3-D-imaging, time-of-arrival real-time locating systems, TOF positron emission tomography, and so on. This addresses the research on the design of new time-to-digital converters characterized by a huge number of channels and precision compliant with detectors' time resolution. In this context, field programmable gate array architectures provide fully digital and completely programmable solutions meeting the demands for flexible setups and speedy prototyping. The innovative contribution provided by the new counter architecture proposed consists of the reduction of the area required for implementation (only 110 SLICEs), with a consequent increase in the number of channels (up to hundreds in a tiny Aritx-7), much higher than the state-of-the-art multiphase solutions available today and of the new complete generation of the time estimates in real time, all while maintaining a state-of-the-art low power consumption and high resolution (up to 150 ps) and precision (up to 68.4 ps r.m.s.).

We present an high-resolution 3D (X,Y,t) imager for time-resolved experiments based on time-to-space conversion. The system uses Cross Delay-Line detectors (CDL) for particle identification and a fully-configurable digital processor based on Field Programmable Gate Arrays (FPGAs) for the 3D image reconstruction. The instrument reaches a spatial resolution of 45 μm FWHM (i.e.,18 μm r.m.s.) and a temporal precision of 15 ps r.m.s.. The detection rate achieved is 10 Mcps, with a dead-time below 7 ns, leading to a global throughput up to 6 Gb/s. In addition to the state-of-the-art performance, the innovative aspect of the presented contribution resides in the complete reconfigurability of the instrument: it is, in fact, the first time that the Time-to-Digital Converter (TDC) used for the time-to-space conversion, has been fully implemented in programmable logic, without the use of dedicated Application Specific Integrated Circuit (ASIC) components. This advancement allows to adapt the instrument to the experimental setup without undergoing impractical hardware modifications.

In a world heading towards applications, in science and industry, based on big data processing, the ability to elaborate streams of data is becoming more important every day. Applications of various natures, ranging from biology to chemistry, from medical imaging to spectroscopy, need systems able to detect, process and store huge amounts of data in real-time. In this context, techniques such as histogramming come into play. Histograms are able to represent data shapes and retrieve statistical information, favoring further processing. This kind of processing is usually done with the help of general purpose processors, relying on temporal computing, with their pros (simplicity and fast operating frequencies) and cons (inability to exploit parallel computation). Both Industry and Academia have, however, proposed many solutions to this need, delivering histogram generators both in full-custom Application-Specific Integrated Circuits (ASICs) and Field-Programmable Gate Array (FPGA) IP-Cores, preferred over processors thanks to their superior parallel computing power. In this work, we present a full FPGA approach to this issue, resulting in a high-performance IP-Core for generating and managing multiple histograms in real time, each supporting a data flow up to 224 MSps, with a strong focus on overall flexibility and area efficiency, using as low as < 250 LUTs and 300 FFs resources for a 16 bit-wide, 4096-bin histogram implementation. The IP-Core has been successfully integrated and validated in a high-performance time-mode application: an FPGA-based Time-to-Digital Converter. The resulting IP-Core is, more in general, a single solution perfectly adaptable to any field of application and FPGA device.

Counting single photons and measuring their arrival time is of crucial importance for imaging and quantum applications that use single photons to outperform classical techniques. The investigation of the coincidence, i.e. correlation, between photons can be used to enhance the resolution of optical imaging techniques or to transmit information using quantum cryptography. Time measurements at the state-of-the-art are performed using Superconducting Nanowire Single Photon Detectors (SNSPDs), the lowest timing jitter single-photon detectors, connected to digital oscilloscopes or digitizers. This method is not well adapted to the ever-increasing and pressing requirement to perform measurements on a high number of channels at the same time. We focus the high-performance measure of the arrival time of photons and their correlation by means of SNSPDs and a 16-channel Time-to-Digital Converter fully implemented in Field Programmable Gate Array (FPGA). In this approach, the photons’ coincidence is analyzed in real-time directly in the FPGA, resulting in a Coincidence Time Resolution (CTR) of 22.8 ps r.m.s.. For the practical benefit of the scientific community, an extended and comprehensive panorama also of comparison with the actual available strategies in this field of applications is offered through a huge number of references.

This study investigated implementation strategies to optimize the precision of Tapped Delay Line (TDL) Time-to-Digital Converters (TDCs) designed for Xilinx 20 nm UltraScale Field-Programmable Gate Arrays (FPGAs). This optimization process aims to bridge the performance gap between FPGA-based TDCs, which are more flexible and suitable for fast prototyping, and the better-performing Application-Specific Integrated Circuit (ASIC) solutions, making FPGA-based TDCs viable for cutting-edge applications. Our key areas of focus included the optimal design of the decoder, the degree of sub-interpolation, and the placement of TDLs, with particular emphasis on the clocking distribution scheme within the Configurable Logic Block (CLB) to minimize the effects of Bubble Errors (BEs) and quantization error. The research led to the development and comparison of multiple TDL TDC solutions implemented on a Kintex UltraScale device (i.e., XCKU040-2FFVA1156E) housed on a KCU105 general-purpose Evaluation Board (EVB). From these, two main solutions emerged: one with high precision and one with low area. The first one was characterized by a Single-Shot Precision (SSP) of 2.64 ps r.m.s., and by Differential and Integral Non-Linearity (DNL/INL) Errors of 0.523 ps and 16.939 ps, respectively, occupying 883 CLBs and 126 kb of Block RAM (BRAM). The second one had an SSP of 3.75 ps r.m.s., a DNL of 0.599 ps, and an INL of 7.151 ps, and it occupies only 259 CLBs and 72 kb of BRAM.