The Field Programmable Gate Array (FPGA) structure poses several constraints that make the implementation of complex asynchronous circuits such as Time–Mode (TM) circuits almost unfeasible. In particular, in Programmable Logic (PL) devices, such as FPGAs, the operation of the logic is usually synchronous with the system clock. However, it can happen that a very high–performance specifications demands to abandon this paradigm and to follow an asynchronous implementative solution. The main driver forcing the use of programmable logic solutions instead of tailored Application Specific Integrated Circuits (ASIC), best suiting an asynchronous design, is the request coming from the research community and industrial R&D of fast–prototyping at low Non Recursive Engineering (NRE) costs. For instance in the case of a high–resolved Time–to–Digital Converter (TDC), a signal clocked at some hundreds of MHz implemented in FPGA allows implementing a TDC with resolution at ns. If a higher resolution is required, the signal frequency cannot be increased further and one of the aces up the designer’s sleeve is the propagation delay of the logic in order to quantize the time intervals by means of a so-called Tapped Delay–Line (TDL). This implementation of TDL–based TDC in FPGAs requires special attention by the designer both in making the best use of all available resources and in foreseeing how signals propagate inside these devices. In this paper, we investigate the implementation of a high–performance TDL–TDC addressed to 28–nm 7–Series Xilinx FPGA, taking into account the comparison between different technological nodes from 65–nm to 20–nm. In this context, the term high–performance means extended dynamic–range (up to 10.3 s), high–resolution and single–shot precision (up to 366 fs and 12 ps r.m.s respectively), low differential and integral non–linearity (up to 250 fs and 2.5 ps respectively), and multi–channel capability (up to 16).

Typically, a time-of-flight (TOF) PET block detector is built using application-specific integrated circuits (ASICs), since they integrate a high number of channels at a reasonable power consumption and into a small area. However, ASICs’ flexibility is limited and prototyping times are long because a semiconductor fabrication process is required in every design iteration. Alternatively, fast terminal (FT) silicon photomultipliers (SiPMs) require a simplified analog front-end in order to achieve time-of-flight (TOF) accuracy. In addition, field-programmable gate arrays (FPGAs) can allocate time-to-digital converters (TDCs) as well as complex digital readout logics. In this work, we propose building TOF-PET block detectors based on FPGAs, FT-SiPMs, and minimal amount of off-the-shelf components. In this way, TOF-PET accuracy is achieved with a full-flexible and fast prototyping solution. We evaluated the coincidence resolving time (CRT), performance degradations due to channel multiplexing, energy resolution, and scintillator pixel encoding performance of SiPM arrays utilizing the proposed approach. Experimental results show minimal timing degradations, when multiplexing FTs. Moreover, simulation results show a low reduction in the singles count rate of multiplexed channels at typical brain-PET radioactive doses.

A new digital instrument for timing of events is presented. It is based on a reconfigurable, high-performance, 16-channel time-to-digital converter implemented in a Xilinx 7 Series 28-nm field programmable gate array device. Each channel provides timestamps with a least significant bit of 2 ps that states the resolution, whereas instead the single-shot precision is below 12.5 ps rms with the possibility of multihit measures at the maximum rate of 20 MHz. The default width of the full-scale range is 157 µs that can be extended at users choosing up to 15 days by means of proper time tagging procedures made available. The instrument achieves performance in terms of precision, resolution, and full-scale range of measurement at the state-of-art of existing solutions. The novelty is that besides performance, the presented instrument is totally reconfigurable by the user both in the hardware and in the firmware parts. Moreover, novel techniques of event acquisition (e.g., level-zero trigger) are introduced. These further features are not present in any other instrument available nor in the literature or in commerce and constitute a difference with respect to all referenced instruments.

The enormous diffusion of Time-Mode circuits, in particular Time-to-Digital Converter (TDC) time measurement circuits, and at the same time the dizzying increase in parallel channels required by the most recent applications, for example in the automotive and digital imaging fields, brings the problem of electromagnetic interference between channels ever more to the fore. This phenomenon, generally known as Cross-Talk (XT), is particularly critical given the increase in the operating frequency and density of systems components, and its effect on the timing parameters in TDC measurements is investigated. Considering the time measurements, XT creates temporal shift on the physical events from which the timestamps are extracted; in this manner, an error in the measurements is generated. In order to detect the XT phenomena, a methodical analysis based on Code-Density Test (CDT) is performed; in this terms, two different typologies of XTs are investigated, which are correlated and uncorrelated XT. Furthermore, a TDC board is used as case study and all the XT sources are detected and classified. Thus, a classification of the importance of the different sources of XT is achived and a solution to minimize the different causes is proposed.

With countless applications, time measurements are among industrial electronics' current most important challenges. This is not a matter of precision, which by now standard architectures have brought in the order of picoseconds and therefore at the physical limits of most common detection systems, but to the number of channels in continuous enormous growth. Just think about time-of-flight (TOF)-based applications like 3-D-imaging, time-of-arrival real-time locating systems, TOF positron emission tomography, and so on. This addresses the research on the design of new time-to-digital converters characterized by a huge number of channels and precision compliant with detectors' time resolution. In this context, field programmable gate array architectures provide fully digital and completely programmable solutions meeting the demands for flexible setups and speedy prototyping. The innovative contribution provided by the new counter architecture proposed consists of the reduction of the area required for implementation (only 110 SLICEs), with a consequent increase in the number of channels (up to hundreds in a tiny Aritx-7), much higher than the state-of-the-art multiphase solutions available today and of the new complete generation of the time estimates in real time, all while maintaining a state-of-the-art low power consumption and high resolution (up to 150 ps) and precision (up to 68.4 ps r.m.s.).

We present a small, portable, plug–and–play time measurement instrument entirely based on Field Programmable Gate Array (FPGA). Its performance is state–of–the–art in terms of the most recent Application–Specific Integrated Circuit (ASIC) solutions of Time–to–Digital Converters (TDCs), and all operating features are fully–programmable. The instrument offers an excellent cost–performance and is suitable for detector test and time correlation measurement applications. More generally, the instrument is very well suited for fast–prototyping of systems where time measures are involved, at low cost and design effort. All the features of the instrument can be easily accessed through either the Graphical User Interface (GUI) or directly from the software Application Programming Interface (API).