The need for fast impedance measurement methods and instruments is necessary for accurate on-line characterization of many bio(electro)chemical systems in which most of the important processes occurs at low frequencies. However, the measurement by means of the traditional single-sine sweep signal is known to be a time-consuming task particularly at ultra-low frequencies. In this work, we demonstrate the synthesis of a structured signal generated from a Gaussian white noise time series such that its power spectral magnitude is relatively flat over a wide bandwidth while maintaining a random phase. Such signal allows the simultaneous measurement for multiple frequencies at once. When used to characterize a precision standard cell, the average deviation of its spectral impedance from that measured using single-sine sweep on a research-grade BioLogic VSP-300 electrochemical station did was about 1.03% over the frequency range 2mHz to 200 kHz. Concurrently, the measurement time was reduced by a factor of 6.08 times compared to the reference instrument. The proposed methodology and processing can be readily adapted to other types of noise for fast impedance measurement.

In this paper, the impact of AlGaN barrier thickness ( $\text{t}_{\mathrm{ AlGaN}}$ ) and substrate leakage on the noise conductance and noise figure in GaN High Electron Mobility Transistor (HEMT) is investigated. The investigation and analysis in this paper are targeting the Low Noise Amplifier (LNA) applications. The noise analysis is carried out using Technology Computer-Aided Design (TCAD) physical simulator. Initially, the DC, RF, and noise simulations are validated against measurements of a GaN device. AlGaN barrier thickness ( $\text{t}_{\mathrm{ AlGaN}}$ ) is varied and its impact on the minimum noise figure (NFmin) is analyzed. It is observed that the NFmin decreases with $\text{t}_{\mathrm{ AlGaN}}$ reduction at the typical bias conditions of LNA. This observation on the impact of $\text{t}_{\mathrm{ AlGaN}}$ on the NFmin follows Fukui’s model, which states that the NFmin decreases with the increase in transconductance. In addition, the impact of the substrate material on noise performance is analyzed. The substrates used for the investigation are Silicon (Si) and Silicon Carbide (SiC). At 40 GHz, it is found that the noise conductance and the NFmin of GaN HEMT on SiC substrate is reduced by 13% and 12%, respectively, in comparison with GaN HEMT on Si substrate. This could be attributed to the lower gate-to-substrate capacitance of the GaN HEMT on SiC substrate.

The recognition of modulation types in received signals is essential for signal detection and demodulation, with broad applications in telecommunications, defense, and wireless communications. This paper introduces a pioneering approach to automatic modulation recognition (AMR) through the development of a highly optimized long short-term memory (LSTM) network. The proposed framework is engineered to capture intricate temporal dependencies within modulated signals, leveraging a gated architecture that effectively mitigates the vanishing gradient problem. This innovation markedly improves recognition accuracy, particularly in low-SNR conditions where traditional methods are often limited. A defining contribution of this work is the introduction of a novel, adaptive temporal-spectral feature learning mechanism, which seamlessly integrates both temporal and spectral characteristics of the signal. This paradigm eliminates the need for manual feature extraction, enhances interpretability, and significantly boosts classification efficiency. Furthermore, the proposed framework is designed for low-complexity deployment, ensuring its scalability and suitability for next-generation wireless networks and real-time communication systems. The proposed architecture is capable of distinguishing between seven modulation classes: BASK, 4-ASK, BFSK, 4-FSK, BPSK, 4-PSK, and 16-QAM. Performance is evaluated across a broad range of signal-to-noise ratios (SNR), from -10 dB to +30 dB, through extensive simulations. Experimental results demonstrate that the model achieves a recognition accuracy of 99.87% at an SNR of -5 dB, outperforming several conventional machine learning techniques, including multi-layer perceptron (MLP), radial basis function (RBF) networks, adaptive neuro-fuzzy inference systems (ANFIS), decision trees (DT), naïve Bayes (NB), support vector machines (SVM), probabilistic neural networks (PNN), k-nearest neighbors (KNN), and ensemble learning models, as well as recurrent neural networks (RNNs). Comparative analysis reveals that the proposed framework outperforms conventional machine learning techniques, with accuracy improvements ranging from 1.77% to 34.03% over the best- and worst-performing methods. Additionally, the proposed model achieves a performance gain of 2.02% over the deep learning (DL)-based RNN, further highlighting its superior capability in AMR.

The advancement of wireless communication toward beyond fifth-generation (B5G) and sixth-generation (6G) standards demands intelligent and scalable signal processing capable of accurate modulation classification under dynamic and noisy channel conditions. Automatic modulation classification (AMC) is essential for spectrum awareness, interference mitigation, and autonomous decision-making. While deep learning (DL) models have improved AMC performance, many conventional architectures face limitations due to sequential processing, high complexity, and reduced robustness in low signal-to-noise ratio (SNR) environments. To address these limitations, this paper presents a novel attention-enhanced hybrid AMC framework that synergistically integrates specialized convolutional layers for efficient temporal feature extraction with a compact transformer encoder for global sequence modeling. The proposed architecture is meticulously tailored to capture the amplitude-phase dynamics inherent in in-phase/quadrature (I/Q) modulated signals while maintaining lightweight design principles. Furthermore, the proposed architecture employs state-of-the-art computational optimizations, including gradient scaling, mixed precision training, and adaptive moment estimation with fixed weight decay (AdamW), to enhance energy efficiency and accelerate convergence. Unlike conventional DL architectures, the proposed technique introduces an efficient parallelized sequence processing strategy that significantly reduces training complexity while preserving robust adaptability across diverse conditions. In contrast to existing hybrid or purely sequential architectures, this design attains high classification fidelity without the need for complex graph-based structures or stacked attention mechanisms, thereby enhancing both model interpretability and practical deployment feasibility. Extensive benchmarking is conducted employing the RadioML 2018.01A dataset, comprising 24 diverse modulation types across various SNR levels, simulating real-world impairments such as fading, oscillator drift, and noise. The proposed framework is rigorously compared against six representative models—recurrent neural networks (RNN), long short-term memory (LSTM), gated recurrent units (GRU), convolutional neural networks-transformer graph neural network (CTGNet), MobileViT, and DeepsigNet—across multiple evaluation criteria. Experimental results consistently validate the effectiveness of the proposed framework, which surpasses leading architectures in accuracy under both static and dynamic (i.e., Jakes-fading) channel conditions. The model achieves an average accuracy improvement of 14.86% over benchmark methods and delivers up to a 38% reduction in inference latency. The study further includes comprehensive ablation analysis, statistical validation, and computational benchmarking, confirming the proposed model as a robust, efficient, and scalable solution for next-generation AMC applications.

Designing a tamper-resistant microchip for small embedded systems is one of the urgent demands of the computing community nowadays due to the immense security challenges arising particularly in massively connected networks. One of the major threats to secure smart card chips is the ability of Side Channel Attacks (SCA), such as Correlation Power Analysis (CPA) and Correlation Instantaneous Frequency Analysis (CIFA) to increase the vulnerability of the secured cipher text to attacks even when the state of the art Advanced Encryption Standard (AES) is used. In this paper we explore the possibility of using chaotic clocking to protect AES chips against CPA and CIFA attacks. Our findings reveal that chaotic clocks, although not random, can effectively provide this protection with a low power envelope. Chaotic clocks derived from two different chaotic systems were used for testing in order to confirm the findings. Two FPGA boards running AES were driven using these chaotic clocks in order to prove the applicability of the proposed security enhancement technique.