The neuromorphic approach of fulfilling brain-like edge intelligence is confronted with three paramount challenges: 1) ever-increasing application demands versus insufficient on-chip resources; 2) diverse data sources and models versus heterogeneous computing paradigms; and 3) adaptation to real scenarios versus absence of on-chip learning. To bridge those gaps in the current research community, this article presents PAICORE, a 537.98-mm $^{2}$ digital neuromorphic processor with a unified computing and learning paradigm. PAICORE is a scalable 1024-core design, integrating over 1.919 million neurons and 4.773 billion synapses on a single chip. PAICORE is implemented in globally asynchronous locally synchronous (GALS) style with a five-level fat up–down quadtree as dedicated network-on-chip (NoC) infrastructure and tiled 2-D chip array as inter-chip architecture. The distributed processing cores fuse the hybrid spiking neural network (SNN), artificial neural network (ANN), and on-chip spike-timing-dependent plasticity (STDP) learning models into a unified description by modular-level reconfiguration. PAICORE achieves the peak performance of 20.74 TSOPS, 41.49 TOPS, and 115.25 GSOPS, with the best energy efficiency of 5.181 TSOPS/W, 10.372 TOPS/W, and 1.222 TSOPS/W for SNN, ANN, and on-chip learning paradigms, respectively. Benefiting from the PAIFLOW software framework, PAICORE hardware platform can be equivalently simulated and efficiently programmed in a large-scale deployment, in accordance with specific optimizing demands for its target multi-paradigm tasks.

Neuromorphic computing, an interdisciplinary field combining neuroscience and computer science, aims to create efficient, bio-inspired systems. Different from von Neumann architectures, neuromorphic systems integrate memory and processing units to enable parallel, event-driven computation. By simulating the behavior of biological neurons and networks, these systems excel in tasks like pattern recognition, perception, and decision-making. Neuromorphic computing chips, which operate similarly to the human brain, offer significant potential for enhancing the performance and energy efficiency of bio-inspired algorithms. This review introduces a novel five-dimensional comparative framework—process technology, scale, power consumption, neuronal models, and architectural features—that systematically categorizes and contrasts neuromorphic implementations beyond existing surveys. We analyze notable neuromorphic chips, such as BrainScaleS, SpiNNaker, TrueNorth, and Loihi, comparing their scale, power consumption, and computational models. The paper also explores the applications of neuromorphic computing chips in artificial intelligence (AI), robotics, neuroscience, and adaptive control systems, while facing challenges related to hardware limitations, algorithms, and system scalability and integration.

Accurate and real-time outdoor localization and pose estimation are critical for various applications, including navigation, robotics, and augmented reality. Apple’s ARKit, a leading AR platform, employs visual–inertial odometry (VIO) and simultaneous localization and mapping (SLAM) algorithms to enable localization and pose estimation. However, ARKit-based systems face positional bias when the device’s camera is obscured, a frequent issue in dynamic or crowded environments. This paper presents a novel approach to mitigate this limitation by integrating position bias correction, context-aware localization, and human–computer interaction techniques into a cohesive interactive module group. The proposed system includes a navigation module, a positioning module, and a front-end rendering module that collaboratively optimize ARKit’s localization accuracy. Comprehensive evaluation across a variety of outdoor environments demonstrates the approach’s effectiveness in improving localization precision. This work contributes to enhancing ARKit-based systems, particularly in scenarios with limited visual input, thereby improving user experience and expanding the potential for outdoor localization applications. Experimental evaluations show that our method improves localization accuracy by up to 92.9% and reduces average positional error by more than 85% compared with baseline ARKit in occluded or crowded outdoor environments.

Hybrid neural networks (HNNs), integrating the strengths of artificial neural networks (ANNs) and spiking neural networks (SNNs), provide a promising solution towards generic artificial intelligence. There is a prevailing trend towards designing unified SNN-ANN paradigm neuromorphic computing chips to support HNNs, but developing platforms to advance neuromorphic computing systems is equally essential. This paper presents the PAIBoard platform, which is designed to facilitate the implementation of HNNs. The platform comprises three main components: the upper computer, the communication module, and the neuromorphic computing chip. Both hardware and software performance measurements indicate that our platform achieves low power consumption, high energy efficiency and comparable task accuracy. Furthermore, PAIBoard is applied in a robot dog for tracking and obstacle avoidance system. The tracking module combines data from ultra-wide band (UWB) transceivers and vision, while the obstacle avoidance module utilizes depth information from an RGB-D camera, which further underscores the potential of our platform to tackle challenging tasks in real-world applications.

Brain-inspired spiking neural network (SNN) has recently attracted widespread interest owing to its event-driven nature and relatively low-power hardware for transmitting highly sparse binary spikes. To further improve energy efficiency, some matrix compression algorithms are used for weight storage. However, the weight sparsity of different layers varies greatly. For a multicore neuromorphic system, it is difficult for the same compression algorithm to adapt to all the layers of SNN model. In this work, we propose a weight density adaptation architecture with hybrid compression method for SNN, named Marmotini. It is a multicore heterogeneous design, including three types of cores to complete computation of different weight sparsity. Benefiting from the hybrid compression method, Marmotini minimizes the waste of neurons and weights as much as possible. Besides, for better flexibility, a reconfigurable core that can be configured to compute convolutional layer or fully connected layer is proposed. Implemented on Xilinx Kintex UltraScale XCKU115 field-programmable gate array (FPGA) board, Marmotini can operate at 150-MHz frequency, achieving 244.6-GSOP/s peak performance and 54.1-GSOP/W energy efficiency at 0% spike sparsity.