In recent years, various platforms have witnessed an unprecedented increase in the number of ransomware attacks targeting hospitals, governments, enterprises, and end-users. The purpose of this is to maliciously encrypt documents and files on infected machines, depriving victims of access to their data, whereupon attackers would seek some sort of a ransom in return for restoring access to the legitimate owners; hence the name. This cybersecurity threat would inherently cause substantial financial losses and time wastage for affected organizations and users. A great deal of research has taken place across academia and around the industry to combat this threat and mitigate its danger. These ongoing endeavors have resulted in several detection and prevention schemas. Nonetheless, these approaches do not cover all possible risks of losing data. In this paper, we address this facet and provide an efficient solution that would ensure an efficient recovery of XML documents from ransomware attacks. This paper proposes a self-healing version-aware ransomware recovery (SH-VARR) framework for XML documents. The proposed framework is based on the novel idea of using the link concept to maintain file versions in a distributed manner while applying access-control mechanisms to protect these versions from being encrypted or deleted. The proposed SH-VARR framework is experimentally evaluated in terms of storage overhead, time requirement, CPU utilization, and memory usage. Results show that the snapshot size increases proportionately with the original size; the time required is less than 120 ms for files that are less than 1 MB in size; and the highest CPU utilization occurs when using the bzip2. Moreover, when the zip and gzip are used, the memory usage is almost fixed (around 6.8 KBs). In contrast, it increases to around 28 KBs when the bzip2 is used.

Decimal arithmetic gains its importance in different applications in the fields of finance and scientific applications. The approach of running decimal arithmetic over binary hardware requires conversions from decimal to binary and from binary to decimal. These conversions produce inexact results that impose financial losses for companies. Therefore, the need for decimal hardware is of high importance. This work proposes decimal addition circuits and presents their realization in complementary metal-oxide semiconductor (CMOS) technology. LTSPICE SPICE simulator software is used to simulate and verify the functionality of the proposed circuits. The circuits are simulated using 45 nm , 65 nm , and 180 nm technologies and compared against existing works in the literature. Due to the lack of existing work in literature and for purpose of comparison, this work also designed five different BCD adders using different existing binary adders in literature. The experimental results show that proposed decimal adder achieves better performance comparing to the other works. For example, for 3-digit operands, the proposed adder shows a power delay product (PDP), in femtojoule (fJ), of 13.88 fJ comparing to 25.38 fJ , 16.01 fJ , 15.24 fJ , 27.49 fJ , and 27.77 fJ PDP for other works.

Elliptic Curve Cryptography (ECC) provides high security with shorter key sizes and higher performance. Internet of Things (IoT) is the interconnected network where a vast number of connected devices require high security to ensure data integrity and privacy. Field programmable gate arrays (FPGAs) are configurable hardware fabrics enhancing the performance of applications. We propose two FPGA-based high performance and lightweight ECC processors for IoT devices. One of the ECC processor is serial with less area and the other is parallel with higher speed. The proposed ECC processors use Edwards curves and perform frequency domain multiplication utilizing FPGA-embedded digital signal processors (DSPs) or lookup tables. The proposed ECC processors work over prime characteristic finite fields of the form GF ((2 ⁿ -1) ⁿ ). Three such prime characteristic finite fields are investigated for each processor: n = 13, 17 and 19, providing the key lengths of 169, 289 and 361 bits, respectively. Synthesis results, targeting different FPGAs, show that the proposed ECC processors outperform similar existing ECC processors in terms of area and speed. For example, over Virtex5 FPGA, compared to the lowest area ECC implementations in the literature over the same finite fields, our serial ECC processor without DSPs occupies 19.07% to 26.06% less slices while being 2.17× to 3.57× faster. Compared to the fastest ECC implementations, our parallel ECC processor without DSPs occupies 20.42% to 27.38% less slices while being 1.76× to 2.22× faster, and our parallel ECC processor that use DSPs is 1.93× to 2.50× faster.