Decimal arithmetic gains its importance in different applications in the fields of finance and scientific applications. The approach of running decimal arithmetic over binary hardware requires conversions from decimal to binary and from binary to decimal. These conversions produce inexact results that impose financial losses for companies. Therefore, the need for decimal hardware is of high importance. This work proposes decimal addition circuits and presents their realization in complementary metal-oxide semiconductor (CMOS) technology. LTSPICE SPICE simulator software is used to simulate and verify the functionality of the proposed circuits. The circuits are simulated using 45 nm , 65 nm , and 180 nm technologies and compared against existing works in the literature. Due to the lack of existing work in literature and for purpose of comparison, this work also designed five different BCD adders using different existing binary adders in literature. The experimental results show that proposed decimal adder achieves better performance comparing to the other works. For example, for 3-digit operands, the proposed adder shows a power delay product (PDP), in femtojoule (fJ), of 13.88 fJ comparing to 25.38 fJ , 16.01 fJ , 15.24 fJ , 27.49 fJ , and 27.77 fJ PDP for other works.

This paper presents a novel approach to designing a CMOS inverter using the Mayfly Optimization Algorithm (MA). The MA is utilized in this paper to obtain symmetrical switching of the inverter, which is crucial in many digital electronic circuits. The MA method is found to have a fast convergence rate compared to other optimization methods, such as the Symbiotic Organisms Search (SOS), Particle Swarm Optimization (PSO), and Differential Evolution (DE). A total of eight different sets of design parameters and criteria were analyzed in Case I, and the results confirmed compatibility between the MA and Spice techniques. The maximum discrepancy in fall time across all design sets was found to be 2.075711 ns. In Case II, the objective was to create a symmetrical inverter with identical fall and rise times. The difference in fall and rise times was minimized based on Spice simulations, with the maximum difference measuring 0.9784731 ns. In Case III, the CMOS inverter was designed to achieve symmetrical fall and rise times as well as propagation delays. The Spice simulation results demonstrated that symmetry had been successfully achieved, with the minimum difference measuring 0.312893 ns and the maximum difference measuring 1.076540 ns. These Spice simulation results are consistent with the MA results. The results conclude that the MA is a reliable and simple optimization technique and can be used in similar electronic topologies.

Gain and offset represent two important measures to determine the accuracy of a comparator. Thus, analysis on these parameters is very important as they offer designers better understanding of the circuit and allow exploring trade-offs during design. In this paper, two methods were presented to derive a set of design equations that describe the gain, sensitivity, offset, and systematic mismatches observed in typical comparator circuits. A three-stage, fast complementary metal-oxide semiconductor (CMOS) comparator structure is analysed and simulated in order to validate the proposed methods. A 0.13 μm CMOS technology is used for simulations with 1.5 V supply voltage. Bisection theorem was used for gain and sensitivity analysis. Simulation results show that high gain improvement can be possible by using the design equations. The input offset voltage, due to mismatch in the width of the metal oxide semiconductor field-effect transistors (MOSFET) (W) and mismatches in the threshold voltages of the N and P type MOSFETs (V_THN, V_THP), is analysed using a proposed balanced method. The same comparator structure is used for the input offset voltage analysis. Simulations show that an offset improvement can be achieved following the design equations found through the proposed method.

Decimal arithmetic is gaining more attention by researchers due to their importance in many human-centric applications. Hardware implementations of decimal arithmetic are preferable over their software counterparts as the former leads in performance especially when it comes to real-time applications. Decimal addition is a main decimal operation as most of the other decimal operation can be implemented using decimal addition. Complementary Metal Oxide Semiconductor (CMOS) technology has the advantage of reducing the average power consumption and the propagation delay in digital systems. Decimal adders can be designed as a ripple carry addition (RCA) structure or as a carry look-ahead addition (CLA) structure with the latter being faster with extra hardware cost. This work proposes two CMOS-based carry look-ahead decimal adders (CLDAs) that can be used within any decimal arithmetic unit. Operands of 1-digit size, 2-digit size, 3-digit size, and 4-digit size are investigated. The Boolean logic for each of the proposed CLDAs is developed and the CMOS realization is provided. The circuit of each of the proposed CLDAs is simulated with 45 nm technology library using the LT-SPICE spice simulation tool. The simulation shows promising results in terms of speed, power, and power delay product (PDP).

Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked input complementary metal-oxide semiconductor (CMOS) transistors which reduce the parasitic resistance in the latch ground path and serve to minimize the latch delay time. The design of each sub-system for the ADC is explained thoroughly, which contains a sample and hold circuit, successive approximation register, charge redistribution types digital-to-analog converter, and the new proposed comparator. The proposed design is implemented using 180 nm CMOS technology with a power supply of 1.2 V. The average inaccuracy in differential non-linearity (DNL) is +0.6/−0.8 LSB (least significant bit), and integral non-linearity (INL) is +0.4/−0.7 LSB. The proposed design exhibits a delay time of 157 ps at 1 MHz clock frequency.