In this study, we designed an asymmetric single-pole double-throw (SPDT) switch that operates at 1.9 -2.4 GHz. To improve the isolation in the Rx mode, which is a disadvantage of asymmetric SPDT switches, a series and parallel resonance structure was proposed and analyzed. The proposed series and parallel resonance structure has been applied to the asymmetric SPDT switch. In addition, in order to secure the power handling capability of the switch, all transistors constituting the switch were designed to be in the on-state in the Tx mode. To verify the feasibility of the proposed structure, an asymmetric switch was designed using 130-nm partially depleted SOI CMOS process. The isolations in Rx and Tx modes were measured to be higher than 28.6 dB and 41.3 dB, respectively. The insertion loss was measured to be less than 1.79 dB in the same frequency range. The input 1-dB compression points (IP1dBs) measured at 2.2 GHz were 6.7 dBm and 38.8 dBm in Rx and Tx modes, respectively. The core size of the designed SPDT switch is 0.27 mm2.

In this study, we proposed a Ka-band CMOS power amplifier (PA) using stacked structure with cascode-like operation to improve output power. The power stage of the PA consists of one common-source (CS) and two common-gate (CG) stages. The CS and the first CG stages were designed as stacked structure. In order to minimize the influence of parasitic inductance caused by the power transistor, an optimization method of the gate capacitor of the CG stage was proposed. In addition, in order to improve the output power and efficiency, the second CG stage was designed to operate close to the cascode operation through optimization of the gate capacitor of the second CG stage. To verify the feasibility of the proposed structure, we designed a Ka-band PA using a 65-nm RFCMOS process. At 29 GHz, the PA achieves P1dB of 22.4 dBm, saturation output power (PSAT) of 22.7 dBm, peak power-added efficiency (PAE) of 25.8%, and small signal gain of 25.2 dB, respectively. The PA is measured with 64-QAM signals, which has a 100-MHz channel bandwidth and a 9.7-dB PAPR. At 29 GHz, the PA achieves output power of 15.6 dBm with -25 dB EVM and the ACLR of -28.5 dBc, respectively.

In this study, we proposed a power amplifier structure with improved efficiency while securing high output power. First, the characteristics of the common-source and stack structures were investigated. In particular, the output power and output impedance characteristics of the stack structure were analyzed compared with the common-source structure. A common-source structure was applied to the driver stage to minimize dc power consumption, and a stack structure was applied to the power stage to ensure high output power. In order to verify the proposed structure, a Ku-band power amplifier was designed using the 65-nm RF CMOS process that provides nine metal layers. At the operating frequency of 15 GHz, saturation output power and maximum power-added efficiency were confirmed to be 22.1 dBm and 17.2%, respectively.

In this study, a 3-bit digital step attenuator (DSA) based on the GaN HEMT process was designed. A distributed structure was adopted to secure stable RF characteristics within a given operating frequency band. To suppress the phase variation according to the attenuation level in the distributed structure, a technique that utilizes a tail capacitor connected in series with a switch transistor has been proposed. The theoretical functionality of the proposed technique has been verified with a numerical analysis. For experimental feasibility verification of the proposed structure, a 3-bit DSA was designed using a 150-nm GaN HEMT process providing two metal layers. The chip size of the designed attenuator was 0.95 mm ² . The measured total attenuation range was 7 dB with 1 dB step. It was confirmed that the measured insertion loss was suppressed to less than 1.7 dB in the range of 26.5 to 40.0 GHz. The RMS amplitude and phase errors were measured to be less than 0.16 dB and 4.87°, respectively.