This letter presents a highly linear 18–42 GHz single-pole double-throw (SPDT) switch based on the traveling-wave concept for 5G applications. An RF switch for 5G applications requires low insertion loss, high isolation, and high linearity in both Tx/Rx modes. To achieve wideband performance and high linearity, the traveling-wave concept and a 150-nm GaN high electron mobility transistor (HEMT) process were used. The equivalent circuit of the SPDT switch was analyzed using the $S$ -parameter to suppress the loss and improve the isolation. The proposed SPDT switch operates with less than 2.0-dB of insertion loss and higher than 32.1-dB of isolation in a frequency range of 18–42 GHz, in both Tx/Rx modes. The measured input 1-dB compression point (IP _1dB ) is 47.5–49.5 dBm at 26–30 GHz. The chip size of the proposed SPDT, including pads, is 3.7 $\times $ 0.51 mm ² .

This study presents a high-linearity K -band single-pole double-throw (SPDT) switch with asymmetric topology in a 65-nm CMOS process for 5G applications. To simultaneously obtain high power-handling capability and high isolation in the Tx and Rx modes, respectively, we propose an SPDT switch using asymmetric topology and the stacked-transistor technique. In both the Tx/Rx modes, the proposed SPDT switch operates with an insertion loss of less than 2.1 dB and isolation better than 22.5 dB in the frequency range 20–25 GHz. At 22 GHz, the measurement results of the input 1-dB compression point (IP $_{\mathrm{1\,dB}})$ are 32.5 and 4.7 dBm in Tx and Rx modes, respectively. The chip core size of the proposed SPDT switch is 0.03 mm $^{2}$ .

In this study, we designed an asymmetric single-pole double-throw (SPDT) switch that operates at 1.9 -2.4 GHz. To improve the isolation in the Rx mode, which is a disadvantage of asymmetric SPDT switches, a series and parallel resonance structure was proposed and analyzed. The proposed series and parallel resonance structure has been applied to the asymmetric SPDT switch. In addition, in order to secure the power handling capability of the switch, all transistors constituting the switch were designed to be in the on-state in the Tx mode. To verify the feasibility of the proposed structure, an asymmetric switch was designed using 130-nm partially depleted SOI CMOS process. The isolations in Rx and Tx modes were measured to be higher than 28.6 dB and 41.3 dB, respectively. The insertion loss was measured to be less than 1.79 dB in the same frequency range. The input 1-dB compression points (IP1dBs) measured at 2.2 GHz were 6.7 dBm and 38.8 dBm in Rx and Tx modes, respectively. The core size of the designed SPDT switch is 0.27 mm2.

In this study, we designed a Ka-band three-stacked CMOS power amplifier (PA) to obtain high output power. Due to the positive feedback path attributed to the complexity of the three-stacked power stage layout, typical capacitive neutralization techniques alone are insufficient to achieve high gain and stability at the same time. To solve this problem, we proposed an LC shunt-feedback technique that can alleviate performance degradation caused by parasitic inductance in the gate node of a power transistor. We designed a PA using a 65-nm RFCMOS process to verify the utility of the proposed structure. At 38 GHz, the proposed PA achieves output 1-dB compression point (OP1dB) of 18.8 dBm, saturation output power (PSAT) of 22.0 dBm, peak power-added efficiency (PAE) of 21.9%, and small signal gain of 32.2 dB, respectively. The PA is measured with 64-quadrature amplitude modulation (QAM) signals, which has a 100-MHz channel bandwidth and a 9.7-dB peak-to-average power ratio (PAPR). At 38GHz, the PA achieves output power of 13.8-dBm with -25-dB error vector magnitude (EVM) and the adjacent channel leakage ratio (ACLR) of -28.1 dBc, respectively. The chip and core sizes of the power amplifier are 0.342 mm2 and 0.096 mm2, respectively.

In this study, we proposed a Ka-band CMOS power amplifier (PA) using stacked structure with cascode-like operation to improve output power. The power stage of the PA consists of one common-source (CS) and two common-gate (CG) stages. The CS and the first CG stages were designed as stacked structure. In order to minimize the influence of parasitic inductance caused by the power transistor, an optimization method of the gate capacitor of the CG stage was proposed. In addition, in order to improve the output power and efficiency, the second CG stage was designed to operate close to the cascode operation through optimization of the gate capacitor of the second CG stage. To verify the feasibility of the proposed structure, we designed a Ka-band PA using a 65-nm RFCMOS process. At 29 GHz, the PA achieves P1dB of 22.4 dBm, saturation output power (PSAT) of 22.7 dBm, peak power-added efficiency (PAE) of 25.8%, and small signal gain of 25.2 dB, respectively. The PA is measured with 64-QAM signals, which has a 100-MHz channel bandwidth and a 9.7-dB PAPR. At 29 GHz, the PA achieves output power of 15.6 dBm with -25 dB EVM and the ACLR of -28.5 dBc, respectively.

In this study, a single-pole double-throw (SPDT) switch for Sub-6 GHz application is designed. In particular, a shunt inductor is connected to the antenna port of the switch for ESD (electrostatic discharge) protection in RF (radio frequency) front end module. The shunt inductor not only serves as an ESD protection device, but also serves as a component of a parallel resonance circuit to suppress insertion loss of the switch. In addition, in order to secure the power handling capability, transistors turned off in the transmit (Tx) mode are implemented as quadruple-gate transistors. An SPDT switch is fabricated using GaAs pHEMT provided in the 500 nm GaAs BiFET process to verify the feasibility of the proposed switch structure. The operating frequency is set from 3 GHz to 5 GHz. The insertion loss and isolation measured in the Tx mode are lower than 0.35 dB and higher than 31.6 dB, respectively. The insertion loss and isolation measured in the Rx mode are lower than 0.32 dB and higher than 33.9 dB, respectively. The chip size including test pads is 0.890 × 0.875 mm².