In this study, an mm-wave band complementary metal–oxide–semiconductor (CMOS) power amplifier (PA) with a two-stage differential structure was designed. An analysis of the designed PA is presented and a new structure is proposed to eliminate the possibility of oscillation in the PA, which has high gain and high output power. The designed driver stage consists of a pair of cascode amplifiers and can be advantageously applied in beamforming systems as the PA phase is converted to 0 $^{\circ}$ /180 $^{\circ}$ with the on/off of a common-gate (CG) bias voltage. The power stage was designed with a three-stacked structure to obtain a high output power. The stability was improved using RC and capacitive feedbacks in the power stage. We implemented the PA using the 65-nm RF CMOS process. The designed PA used supply voltages of 2.0 and 3.3 V for the driver and power stages, respectively, and its saturated output power was measured as 24.7 dBm at 22.0 GHz. In this case, P $_{\mathrm{1\,dB}}$ was 20.6 dBm and the peak power added efficiency (PAE) was 26.0%.

This letter presents a highly linear 18–42 GHz single-pole double-throw (SPDT) switch based on the traveling-wave concept for 5G applications. An RF switch for 5G applications requires low insertion loss, high isolation, and high linearity in both Tx/Rx modes. To achieve wideband performance and high linearity, the traveling-wave concept and a 150-nm GaN high electron mobility transistor (HEMT) process were used. The equivalent circuit of the SPDT switch was analyzed using the $S$ -parameter to suppress the loss and improve the isolation. The proposed SPDT switch operates with less than 2.0-dB of insertion loss and higher than 32.1-dB of isolation in a frequency range of 18–42 GHz, in both Tx/Rx modes. The measured input 1-dB compression point (IP _1dB ) is 47.5–49.5 dBm at 26–30 GHz. The chip size of the proposed SPDT, including pads, is 3.7 $\times $ 0.51 mm ² .

This study presents a high-linearity K -band single-pole double-throw (SPDT) switch with asymmetric topology in a 65-nm CMOS process for 5G applications. To simultaneously obtain high power-handling capability and high isolation in the Tx and Rx modes, respectively, we propose an SPDT switch using asymmetric topology and the stacked-transistor technique. In both the Tx/Rx modes, the proposed SPDT switch operates with an insertion loss of less than 2.1 dB and isolation better than 22.5 dB in the frequency range 20–25 GHz. At 22 GHz, the measurement results of the input 1-dB compression point (IP $_{\mathrm{1\,dB}})$ are 32.5 and 4.7 dBm in Tx and Rx modes, respectively. The chip core size of the proposed SPDT switch is 0.03 mm $^{2}$ .

In this paper, a CMOS antiphase power amplifier (PA) is presented with a multigate transistor (MGTR) technique that improves its linearity. The drive stage of the PA is biased in the subthreshold region, such as in class C, to realize the antiphase technique. The nonlinearity of the power stage of the PA is canceled out using the third-order intermodulation distortion and phase distortion of the drive stage. The cancellation effect is further optimized and enhanced without any performance degradation with the aid of the proposed MGTR technique at the drive stage. Unlike the traditional technique, which suppresses the nonlinearity of the PA, the MGTR technique is used to enhance the nonlinearity of the drive stage to cancel out the significant nonlinearity of the power stage. The proposed PA is fabricated with a 180-nm RF CMOS process and used to verify the linearity by WCDMA and LTE signals. The measurement results show an average output power of 25.8 dBm, PAE of 28%, and error vector magnitude of 3% at 1.85 GHz for the WCDMA. The PA also shows an average output power of 24.4-25.8 dBm at 1.7-2.0 GHz for the WCDMA. The PA is verified for LTE signals with 10 MHz of bandwidth/16 QAM and with 20 MHz of bandwidth/64 QAM. No digital predistortion or off-chip components are utilized.

In this study, we designed an asymmetric single-pole double-throw (SPDT) switch that operates at 1.9 -2.4 GHz. To improve the isolation in the Rx mode, which is a disadvantage of asymmetric SPDT switches, a series and parallel resonance structure was proposed and analyzed. The proposed series and parallel resonance structure has been applied to the asymmetric SPDT switch. In addition, in order to secure the power handling capability of the switch, all transistors constituting the switch were designed to be in the on-state in the Tx mode. To verify the feasibility of the proposed structure, an asymmetric switch was designed using 130-nm partially depleted SOI CMOS process. The isolations in Rx and Tx modes were measured to be higher than 28.6 dB and 41.3 dB, respectively. The insertion loss was measured to be less than 1.79 dB in the same frequency range. The input 1-dB compression points (IP1dBs) measured at 2.2 GHz were 6.7 dBm and 38.8 dBm in Rx and Tx modes, respectively. The core size of the designed SPDT switch is 0.27 mm2.