Toom–Cook-n multiplication is an efficient large-width multiplication algorithm based on a divide-and-conquer strategy, widely used in modular multiplication operations for cryptographic algorithms. Theoretically, as the degree n increases, Toom–Cook-n can split the multiplicands into more sub-terms to further enhance the performance of the multiplier. However, constrained by the computational burden brought by the growing size of the interpolation matrix as the degree increases, current research predominantly focuses on Toom–Cook-4 and Toom–Cook-3. This paper proposes a Montgomery modular multiplication design based on Toom–Cook-5, which alleviates the computational difficulty of the interpolation step by introducing an interpolation matrix pre-simplification strategy. Additionally, the design incorporates and optimizes carry–save adder and Karatsuba multiplication, enabling Toom–Cook-5 multiplication to be applied in practical and efficient hardware implementation. This paper presents the ASIC implementation results of the hardware architecture under a 90nm process, demonstrating superior performance compared to previous works.

Real-time Direction of Arrival (DOA) estimation demands high computational throughput and numerical precision. Consequently, dedicated hardware accelerators are essential. This paper presents an architecture to accelerate the MUSIC algorithm using an improved complex bilateral Jacobi eigenvalue decomposition (EVD). First, we design a triangular systolic array for Hermitian matrices. It employs an output-stationary dataflow to enable efficient parallel covariance computation. Second, we propose an enhanced EVD algorithm. It replaces CORDIC approximations with direct analytical rotations. This significantly improves numerical stability and accuracy. Third, we introduce hardware optimizations. These include unit reuse, integrated termination conditions, and pre-stored steering vectors. These measures reduce resource consumption while maintaining full functionality. Experiments on a Xilinx Virtex-6 platform validate the design. The architecture achieves a root mean square error (RMSE) below $0.24°$ with 300 snapshots. Processing latency is only 76.17 µs. The design utilizes 10,775 LUTs and 73 DSP slices. This work balances accuracy, speed, and efficiency. It offers a practical solution for real-time, high-precision DOA systems.

Infrared small target detection is a key technology with a wide range of applications, and the complex background and low signal-to-noise ratio characteristics of infrared images can greatly increase the difficulty and error rate of small target detection. In this paper, an uncertainty measurement method based on local component consistency is proposed to suppress the complex background and highlight the detection target. The method analyzes the local signal consistency of the image. It then constructs a confidence assignment function and uses the mutation entropy operator to measure local uncertainty. Then, the target energy information is introduced through an energy-weighting function to further enhance the signal. Finally, the target is extracted using an adaptive threshold segmentation algorithm. The experimental results show that the algorithm can effectively detect small infrared targets in complex backgrounds. And, the algorithm is at the leading edge in terms of performance; the processing frame rate can reach 3051 FPS (frame per second), 96 FPS, and 54 FPS for image data with a resolution of 256 × 256, 1920 × 1080, and 2560 × 1440, respectively.