Hardware Trojan detection through side-channel analysis in physical chips is very challenging due to the presence of manufacturing process variations. Numerous Trojan detection approaches are in the literature. However, most of them are limited to netlist level identification and unable to explain the process variation issue in post-silicon chips. In this work, we propose a new detection technique with delay side-channel analysis that can detect all types of Trojans under the presence of high process variations. The technique is termed as zero delay deviation (ZDD) that is capable of diminishing the effect of all variations and other noise sources to identify the Trojan presence in chips. The ZDD approach is achieved by 1) a novel equal-delay circuit partitioning, 2) placing a highly secured camouflaged ring oscillator PUF per partition to generate equal-delay challenge-response pairs that delivers the knowledge of variation trends, 3) generating Identical Delay (ID) neighboring pairs for both, partitions and PUF designs that ensure nullifying the variation effects upon comparing them. The ZDD is examined through an intra-referencing of ID pairs with PUF-RD pairs in ISCAS’85 and 89 benchmarks. 10,000 virtual chips are generated by Monte Carlo simulation considering all physical characteristics of a real chip. Results demonstrate that the proposed approach can successfully detect Trojans even if it consists of a single gate. A comparison to the state-of-the-art shows the method superiority over others.

Autonomous driving has emerged as a rapidly advancing field in both industry and academia over the past decade. Among the enabling technologies, computer vision (CV) has demonstrated high accuracy across various domains, making it a critical component of autonomous vehicle systems. However, CV tasks are computationally intensive and often require hardware accelerators to achieve real-time performance. Field Programmable Gate Arrays (FPGAs) have gained popularity in this context due to their reconfigurability and high energy efficiency. Numerous researchers have explored FPGA-accelerated CV solutions for autonomous driving, addressing key tasks such as lane detection, pedestrian recognition, traffic sign and signal classification, vehicle detection, object detection, environmental variability sensing, and fault analysis. Despite this growing body of work, the field remains fragmented, with significant variability in implementation approaches, evaluation metrics, and hardware platforms. Crucial performance factors, including latency, throughput, power consumption, energy efficiency, detection accuracy, datasets, and FPGA architectures, are often assessed inconsistently. To address this gap, this paper presents a comprehensive literature review of FPGA-accelerated, vision-based autonomous driving systems. It systematically examines existing solutions across sub-domains, categorizes key performance factors and synthesizes the current state of research. This study aims to provide a consolidated reference for researchers, supporting the development of more efficient and reliable next generation autonomous driving systems by highlighting trends, challenges, and opportunities in the field.